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company confidential ? 1 data sheet ? 2000-2009 by atheros communications, inc. all rights reserved. atheros ? , atheros driven ? , atheros xr ? , driving the wireless future ? , rocm ? , super ag ? , super g ? , total 802.11n ? , and wake on wireless ? are registered by atheros communications, inc. atheros sst?, signal-sustain technology?, the air is cleaner at 5-ghz?, xspan?, wireless future. unleashed now.?, and 5-up? are trademarks of atheros communications, inc. the atheros logo is a registered trademark of atheros communications, inc. all other tr ademarks are the property of their respective holders. subject to change without notice. october 2009 AR9223 single-chip 2x2 mimo mac/bb/radio with pci interface for 802.11n 2.4 ghz wlans general description the atheros AR9223 is a highly integrated single-chip solution fo r 2.4 ghz 802.11n-ready wireless local area networks (wlans) that enables high-performance 2x2 mimo configurations for wireless station applications demanding robust link quality and maximum throughput and range. the AR9223 integrates a multi-protocol mac, baseband processor, analog-to-digital and digital-to-analog (adc/ dac) converters, 2x2 mimo radio transceiver, and pci interface in an all-cmos device for low power and small form factor applications. the AR9223 implements half-duplex ofdm, cck, and dsss baseband processing, supporting up to 130 mbps for 20 mhz and 300 mbps for 40 mhz channel operations respectively, and ieee 802.11b/g data rates. additional features include signal detection, automatic gain control, frequency offset estimati on, symbol timing, and channel estimation. the AR9223 mac supports the 802.11 wireless mac protocol, 802.11i security, receive and transmit filtering, error recovery, and quality of service (qos). the AR9223 supports two simultaneous traffic streams using up to two integrated transmit chains and receive chains for high throughput and range performance. transmit chains combine baseband in-phase (i) and quadrature (q) signals, convert them to the desired frequency, and drive the rf signal to multiple antennas. he receiver converts an rf signal to baseband i and q outputs. the frequency synthesizer supports one-mhz steps to match frequencies defined by ieee 802.11b/g/n specifications. the AR9223 supports frame data transfer to and from the host using a pci interface that provides interrupt generation and reporting, power save, and status reporting. other external interfaces include serial eeprom and gpios. the AR9223 interoperates with stan dard legacy 802.11b/g devices. features all-cmos mimo solution interoperable with ieee 802.11b/g/n wlans 2x2 mimo technology improves effective throughput and range over existing 802.11b/g products supports spatial multiplexing, cyclic-delay diversity (cdd), and maximal ratio combining (mrc) 2.4 ghz wlan mac/bb processing bpsk, qpsk, 16 qam, 64 qam, dbpsk, dqpsk, and cck modulation schemes data rates of up to 130 mbps for 20 mhz channels and 300 mbps for 40 mhz channels wireless multimedia enhancements quality of service support (qos) 802.11e-compatible bursting support for ieee 802.11e, h, and i standards wep, tkip, and aes hardware encryption 20 and 40 mhz channelization 32-bit 0?33 and 66-mhz pci 2.3 interface reduced (short) guard interval frame aggregation block ack ieee 1149.1 standard test access port and boundary scan architecture supported 337-pin, 12 mm x 12 mm bga package AR9223 system block diagram baseband serial eeprom gpios pci mac/ configuration control/ memory host and peripheral interface rx radio tx radio bb filters in/out mux bb filters in/out mux bias/control frequency synthesizers dac adc 2.4 ghz 2x2 radio front- end circuits AR9223 40 mhz crystal dac adc rx radio tx radio do not copy free datasheet http://www.datasheet-pdf.com/
2 ? AR9223 single-chip 2x2 mimo mac/bb/radio for 802.11n wlans atheros communications, inc. 2 ? october 2009 company confidential do not copy free datasheet http://www.datasheet-pdf.com/
atheros communications, inc. AR9223 single-chip 2x2 mimo mac/bb/radio for 802.11n wlans ? 3 company confidential october 2009 ? 3 table of contents general description ........................................ 1 features ............................................................ 1 AR9223 system block diagram .................... 1 1 pin descriptions ............................ 5 2 functional description ............... 13 2.1 overview ................................................. 13 2.1.1 configuration block ................... 13 2.1.2 AR9223 address map ............... 13 2.1.1 serial eeprom interface ........... 14 2.1.1 eeprom auto-sizing mechanism 14 2.1.2 eeprom read/write protection mechanism ................................... 14 2.2 reset ......................................................... 14 2.3 gpio ........................................................ 14 2.4 led .......................................................... 14 2.5 pci host interface .................................. 14 2.5.1 pci registers ............................... 15 2.6 signal description .................................. 15 2.7 host interface unit interrupts .............. 15 3 medium access control (mac) 17 3.1 overview ................................................. 17 3.2 descriptor ................................................ 17 3.3 descriptor format .................................. 18 3.4 queue control unit (qcu) .................. 31 3.4.1 dcf control unit (dcu) ........... 31 3.5 protocol control unit (pcu) ................ 31 4 digital phy block ....................... 33 4.1 overview ................................................. 33 4.2 802.11n (mimo) mode .......................... 33 4.2.1 transmitter (tx) .......................... 33 4.2.2 receiver (rx) ............................... 33 4.3 802.11 a/b/g legacy mode .................. 34 4.3.1 transmitter .................................. 34 4.3.2 receiver ........................................ 34 5 radio block .................................. 35 5.1 receiver (rx) block ................................ 35 5.2 transmitter (tx) block .......................... 36 5.3 synthesizer (synth) block ................. 37 5.4 bias/control (bias) block ................... 37 6 register descriptions ..................39 6.1 host pci configuration space registers 39 6.1.1 vendor id .................................... 40 6.1.2 device id ..................................... 40 6.1.3 command .................................... 40 6.1.4 status ............................................ 41 6.1.5 revision id .................................. 42 6.1.6 class code ................................... 42 6.1.7 cache line size ........................... 42 6.1.8 latency timer ............................. 42 6.1.9 header type ................................ 43 6.1.10 base address ............................... 43 6.1.11 subsystem vendor id ................ 43 6.1.12 subsystem id .............................. 43 6.1.13 capabilities pointer (cap_ptr) 44 6.1.14 interrupt line (int_line) ....... 44 6.1.15 interrupt pin (int_pin) ............ 44 6.1.16 mingnt ......................................... 44 6.1.17 maxlat ......................................... 44 6.2 AR9223 internal regi ster descriptions 45 6.2.1 general dma and rx-related registers ....................................... 45 6.2.2 beacon handling ........................ 64 6.2.3 qcu registers ............................. 66 6.2.4 dcu registers ............................. 72 6.2.5 eeprom interface registers .... 82 6.2.6 host interface registers ............. 82 6.2.7 rtc interface registers ............. 92 6.2.8 mac pcu registers ................... 95 6.2.9 ms counter and rx/tx latency (mac_pcu_usec_latency) 99 7 electrical characteristics ..........121 7.1 absolute maximum ratings .............. 121 7.2 recommended operating conditions 121 7.3 radio receiver characteristics .......... 122 7.4 radio transmitter characteristics ..... 123 7.5 synthesizer characteristics ................ 124 7.6 power consumption parameters ...... 124 do not copy free datasheet http://www.datasheet-pdf.com/
4 ? AR9223 single-chip 2x2 mimo mac/bb/radio for 802.11n wlans atheros communications, inc. 4 ? october 2009 company confidential 8 ac specifications ...................... 125 8.1 pci interface timing ........................... 125 8.2 pci_clk specifications ...................... 125 8.3 pci clock specifications ..................... 125 8.3.10 pci timing parameters ............ 126 8.4 eeprom timing .................................. 126 9 package dimensions ................. 127 10 ordering information .............. 129 do not copy free datasheet http://www.datasheet-pdf.com/
atheros communications, inc. AR9223 single-chip 2x2 mimo mac/bb/radio for 802.11n wlans ? 5 company confidential october 2009 ? 5 1. pin descriptions this section contains a package pinout (see table 1-1 , table 1-2 , and table 1-3 ) and a tabular listing of the signal descriptions. this nomenclature is used for signal names: this nomenclature is used for signal types: nc no connection should be made to this pin _l at the end of the signal name, indicates active low signals p at the end of the signal name, indicates the positive side of a differential signal n at the end of the signal name indicates the negative side of a differential signal i digital input signal i/o a digital bidirectional signal ia analog input signal ih input signals with weak internal pull-up, to prevent signals from floating when left open il input signals with weak internal pull-down, to prevent signals from floating when left open o a digital output signal oa an analog output signal od a digital output signal with open drain p a power or ground signal do not copy free datasheet http://www.datasheet-pdf.com/
6 ? AR9223 single-chip 2x2 mimo mac/bb/radio for 802.11n wlans atheros communications, inc. 6 ? october 2009 company confidential table 1-1. pin assignments (1?12) 123456789101112 a gnd biasref gnd nc nc nc nc avdd33 rf2in p_1 rf2inn_1 rf2outn_1 rf2outp_1 b rst_l gnd avdd12 nc gnd nc gnd avdd33 a vdd12 gnd pa2biasn_1 pa2biasp_1 c av d d 1 2 av d d 3 3 d rf2outp_0 pa2biasp_0 e rf2outn_0 gnd f rf2inn_0 pa2biasn_0 gnd gnd gnd gnd gnd gnd gnd g rf2inp_0 gnd gnd gnd gnd gnd gnd gnd gnd h av d d 3 3 av d d 3 3 gnd gnd gnd gnd gnd gnd gnd j nc avdd12 gnd gnd gnd gnd gnd gnd gnd k nc gnd gnd gnd gnd gnd gnd gnd gnd l nc nc gnd gnd gnd gnd gnd gnd gnd m nc nc gnd gnd gnd gnd gnd gnd gnd n av d d 1 2 p d e t _ 0 gnd gnd gnd gnd gnd gnd gnd p nc gnd gnd gnd gnd gnd gnd gnd gnd r nc nc gnd gnd gnd gnd gnd gnd gnd t nc dvdd33 gnd gnd gnd gnd gnd gnd gnd u pci_req_l pci_int_l gnd gnd gnd gnd gnd gnd gnd v pci_mode pci_ad31 gnd gnd gnd gnd gnd gnd gnd w pci_gnt_l pci_ad29 y pci_ad30 pci_ad28 aa pci_ad27 dvdd12 ab swcom1 gnd dvdd33 gpio0 gpio1 gpio3 pci_clk d vdd12 pci_ad25 pci_ad23 dvdd12 pci_ad20 ac gnd swcom0 nc gnd gpio2 pci_ad26 pci_ad24 dvdd33 pci_cbe3_l pci_idsel pci_ad21 pci_ad22 do not copy free datasheet http://www.datasheet-pdf.com/
atheros communications, inc. AR9223 single-chip 2x2 mimo mac/bb/radio for 802.11n wlans ? 7 company confidential october 2009 ? 7 table 1-2. pin assignments (13?23) 13 14 15 16 17 18 19 20 21 22 23 a avdd12 xlnabias_0 xpa2bias_1 avdd33 nc gnd gnd xtali xtalo gnd gnd b pdet_1 xlnabias_1 xpa2bias_0 avdd12 nc g nd gnd avdd12_xtal avdd33_xtal gnd gnd c nc gnd d nc gnd e gnd gnd f gnd gnd gnd gnd gnd gnd pci_ad0 pci_ad1 g gnd gnd gnd gnd gnd gnd pci_ad2 pci_ad3 h gnd gnd gnd gnd gnd gnd dvdd33 dvdd12 j gnd gnd gnd gnd gnd gnd pci_ad4 pci_ad6 k gnd gnd gnd gnd gnd gnd pci_cbe0_l pci_ad5 l gnd gnd gnd gnd gnd gnd pci_ad9 pci_ad7 m gnd gnd gnd gnd gnd gnd pci_ad10 pci_ad8 n gnd gnd gnd gnd gnd gnd eprm_sda eprm_sck p gnd gnd gnd gnd gnd gnd gpio8 gpio9 r gnd gnd gnd gnd gnd gnd pci_ad12 pci_ad11 t gnd gnd gnd gnd gnd gnd dvdd12 dvdd33 u gnd gnd gnd gnd gnd gnd gnd pci_ad13 v gnd gnd gnd gnd gnd gnd pci_ad15 pci_ad14 w gpio7 pci_devsel_l y gpio5 gpio6 aa pci_stop_l gpio4 ab dvdd33 swcom3 pci_par dvdd12 pci_ad16 pci_frame _l pci_rst_l dvdd33 pci_pme_l gnd pci_cbe1_l ac pci_ad19 swcom2 pci_ad18 pci_ad17 pci_cbe2_l pci_irdy_l pci_trdy_l pci_clkrun_l pci_serr_l pci_perr_l gnd do not copy free datasheet http://www.datasheet-pdf.com/
8 ? AR9223 single-chip 2x2 mimo mac/bb/radio for 802.11n wlans atheros communications, inc. 8 ? october 2009 company confidential table 1-3. signal-to-pin relationships and descriptions symbol pin type description pci pci_ad31 v2 i/o multiplexed address and da ta bus. during the first clock of a transaction, ad[31:0] contains a physical byte address. during subsequent clocks, it contains data. pci_ad30 y1 i/o pci_ad29 w2 i/o pci_ad28 y2 i/o pci_ad27 aa1 i/o pci_ad26 ac6 i/o pci_ad25 ab9 i/o pci_ad24 ac7 i/o pci_ad23 ab10 i/o pci_ad22 ac12 i/o pci_ad21 ac11 i/o pci_ad20 ab12 i/o pci_ad19 ac13 i/o pci_ad18 ac15 i/o pci_ad17 ac16 i/o pci_ad16 ab17 i/o pci_ad15 v22 i/o pci_ad14 v23 i/o pci_ad13 u23 i/o pci_ad12 r22 i/o pci_ad11 r23 i/o pci_ad10 m22 i/o pci_ad9 l22 i/o pci_ad8 m23 i/o pci_ad7 l23 i/o pci_ad6 j23 i/o pci_ad5 k23 i/o pci_ad4 j22 i/o pci_ad3 g23 i/o pci_ad2 g22 i/o pci_ad1 f23 i/o pci_ad0 f22 i/o pci_cbe3_l ac9 i/o pci multiplexed bus command and byte enables. du ring a transaction address phase, these signals define the bus command. during the data phase, they are used as byte enables. pci_cbe2_l ac17 i/o pci_cbe1_l ab23 i/o pci_cbe0_l k22 i/o do not copy free datasheet http://www.datasheet-pdf.com/
atheros communications, inc. AR9223 single-chip 2x2 mimo mac/bb/radio for 802.11n wlans ? 9 company confidential october 2009 ? 9 pci_clk ab7 i pci clock, input for target, output for master pci_clkrun_l ac20 o provides for star ting and stopping the pci clock pci_devsel_l w23 i/o pci device select pci_frame_l ab18 i/o pci frame pci_gnt_l w1 i pci grant pci_idsel ac10 i pci id select pci_int_l u2 o pci interrupt pci_irdy_l ac18 i/o pci initiator ready pci_mode v1 i selects between pci and cardbus interface 0cardbus 1pci (default) pci_par ab15 i/o pci parity pci_perr_l ac22 i/o pci parity error pci_pme_l ab21 o pci power management pci_req_l u1 o pci request pci_rst_l ab19 ih pci reset pci_serr_l ac21 i/o pci system error pci_stop_l aa22 i/o pci stop pci_trdy_l ac19 i/o pci target ready radio biasref a2 ia biasref voltage is 310 mv; must connect a 6.19 k 1% resistor to ground rf2inn_0 f1 ia differential rf in puts at 2.4 ghz for chain 0. use one side for single-ended input. rf2inp_0 g1 ia rf2inn_1 a10 ia differential rf in puts at 2.4 ghz for chain 1. use one side for single-ended input. rf2inp_1 a9 ia rf2outn_0 e1 oa differential 2.4 ghz rf power amplifier output for chain 0 rf2outp_0 d1 oa rf2outn_1 a11 oa differential 2.4 ghz rf power amplifier output for chain 1 rf2outp_1 a12 oa table 1-3. signal-to-pin relationships and descriptions (continued) symbol pin type description do not copy free datasheet http://www.datasheet-pdf.com/
10 ? AR9223 single-chip 2x2 mimo mac/bb/radio for 802.11n wlans atheros communications, inc. 10 ? october 2009 company confidential analog interface pa2biasn_0 f2 oa external bias for 2.4 ghz for chain 0 pa2biasp_0 d2 oa pa2biasn_1 b11 oa external bias for 2.4 ghz for chain 1 pa2biasp_1 b12 oa pdet_0 n2 ia power detector pdet_1 b13 ia xlnabias_0 a14 oa external lna bias xlnabias_1 b14 oa xpa2bias_0 b15 oa external bias for 2.4 ghz xpa2bias_1 a15 external switch control swcom0 ac2 o common switch control swcom1 ab1 o swcom2 ac14 o swcom3 ab14 o general rst_l b1 i reset for the AR9223 xtali a20 i 40 mhz crystal. a pull up resi stor may be needed on the xtali pin, please refer to the reference design schematic. when using an external clock, th e xtali pin is grounded and the xtalo pin should be driven with a square wave clock that has -0.2v < vil < 0.2v and 1v < vih < 3.3v. the dc voltage level of xtalo sh ould be approxim ately 0.6v. the external clock driving xtalo must have sharp rise and fall times to reduce jitter. xtalo a21 i/o gpio gpio0 ab4 i/o general purpose gpio pins the pins gpio0 through gpio2 and gpio4 are multiplexed pins that default to the jtag interface. gpio1 ab5 i/o gpio2 ac5 i/o gpio3 ab6 i/o gpio4 aa23 i/o gpio5 y22 i/o gpio6 y23 i/o gpio7 w22 i/o gpio8 p22 i/o gpio9 p23 i/o table 1-3. signal-to-pin relationships an d descriptions (continued) symbol pin type description do not copy free datasheet http://www.datasheet-pdf.com/
atheros communications, inc. AR9223 single-chip 2x2 mimo mac/bb/radio for 802.11n wlans ? 11 company confidential october 2009 ? 11 serial eeprom eprm_sck n23 o serial eeprom clock eprm_sda n22 i/o serial eeprom data table 1-3. signal-to-pin relationships and descriptions (continued) symbol pin type description symbol pin description power avdd12 a13, b3, b9, b16, c1, j2, n1 analog 1.2 v power supply avdd12_xtal b20 supply voltage for the crystal oscillator avdd33 a8, a16, b8, c2, h1, h2 analog 3.3 v power supply avdd33_xtal b21 supply voltage for the crystal oscillator dvdd12 h23, t22, aa2, ab8, ab11 , ab16 digital 1.2 v power supply dvdd33 h22, t2, t23, ab3, ab13, ab 20, ac8 digital 3.3 v power supply gnd a1, a3, a18, a19, a22, a23, b2, b5, b7, b10, b18, b19, b22, b23, c23, d23, e2, e22, e23, f6, f7, f8, f9, f10, f11, f12, f13, f14, f15, f16, f17, f18, g2, g6, g7, g8, g9, g10, g11, g12, g13, g14, g15, g16, g 17, g18, h6, h7, h8, h9, h10, h11, h12, h13, h14, h15, h16, h17, h18, j6, j7, j8, j9, j10, j11, j12, j13, j14, j15, j16, j17, j18, k2, k6, k7, k8, k9, k10, k11, k12, k13, k14, k15, k16, k17, k18, l6, l7, l8, l9, l10, l11, l12, l13, l14, l15, l16, l17, l18, m6, m7, m8, m9, m10, m11, m12, m13, m14, m15, m16, m17, m18, n6, n7, n8, n9, n10, n11, n12, n13, n14, n15, n16, n17, n18, p2, p6, p7, p8, p9, p10, p1 1, p12, p13, p 14, p15, p16, p17, p18, r6, r7, r8, r9, r10, r1 1, r12, r13, r14, r15, r16, r17, r18, t6, t7, t8, t9, t10, t1 1, t12, t13, t14, t15, t16, t17, t18, u6, u7, u8, u9, u10, u11, u12, u13, u14, u15, u16, u17, u18, u22, v6, v7, v8, v9, v10, v11, v12, v13, v14, v15, v16, v17, v18, ab2, ab22, ac1, ac4, ac23 gnd nc a4, a5, a6, a7, a17, b4, b6, b17,c22, d22, j1, k1, l1, l2, m1, m2, p1, r1, r2, t1, ac3 no connect do not copy free datasheet http://www.datasheet-pdf.com/
12 ? AR9223 single-chip 2x2 mimo mac/bb/radio for 802.11n wlans atheros communications, inc. 12 ? october 2009 company confidential do not copy free datasheet http://www.datasheet-pdf.com/
atheros communications, inc. AR9223 single-chip 2x2 mimo mac/bb/radio for 802.11n wlans ? 13 company confidential october 2009 ? 13 2. functional description 2.1 overview the AR9223 consists of four major functional blocks: pci interface, mac, digital phy, and radio. the ieee 802.11 mac functionality is partitioned between the host and the AR9223. ieee 802.11 mac data service is provided by the mac of the AR9223, while the host software, with the aid of the AR9223 mac, controls tx and rx queue processing. the baseband digital processing functions are implemented by the digital phy of the AR9223. the radio frequency (rf) and baseband analog processing are provided by the integrated radio. the physical layer (phy) is partitioned between the baseband processor and the radio. the configuration block, pll, adc, dac, eeprom interface, jtag, antenna control, led controls and gpio complete the AR9223 functionality. see figure 2-1 . 2.1.1 configuration block the configuration block provides control, status, and configuration, for each major functional block. this block contains registers accessed by other blocks and by the host using the pci interface. see ?register descriptions? on page 39 for more information. 2.1.2 AR9223 address map internal registers of the various functional blocks and the AR9223 peripheral interface are accessible with the host using the pci interface. these register locations are defined as offset addresses. the combination of the host base address and the offset address allows access to a particular internal register. table 2-1 lists the offset addresses for the AR9223 internal registers and peripheral interface. figure 2-1. functional block diagram of the AR9223 table 2-1. offset addresses offset location usage description 0x0000?0x07fc mac dma general dma access 0x0800?0x0ffc mac dma qcu registers contr ol and status register for qcu 0x1000?0x1ffc dcu registers control and status register for dcu 0x2000?0x3ffc eeprom acce ss register memory locations of eeprom are mapped to this address range and allow access to eeprom 0x4000?0x4ffc host interface control and st atus register for host interface 0x8000?0x98fc pcu registers control and status register for pcu do not copy free datasheet http://www.datasheet-pdf.com/
14 ? AR9223 single-chip 2x2 mimo mac/bb/radio for 802.11n wlans atheros communications, inc. 14 ? october 2009 company confidential 2.1.1 serial eeprom interface the AR9223 provides a serial interface to access an external eeprom. the eeprom interface provides configuration space registers and configuration- and vendor-specific information. the off-chip eeprom can be: a 32-kb device, organized as 2,048 entries of 16 bits each (2,048x16) an 64-kb device, organi zed as 4,096 entries of 16 bits each (4,096x16) the hardware automatically detects eeprom size. the eeprom addressing is 16 bits wide, with each 16-bit eeprom mapped into the AR9223's register space. each 32-bit aligned address corresponds to a unique eeprom location. because the host interface supports 32-bit register accesses and ignores the two least significant address bits, the address offset provided by the host interface corresponds to four times the eeprom location. at reset, some pci configuration registers load from the eeprom while others are programmed by the host or initialized by AR9223 hardware. to ensure that the eeprom contents are valid, a 16-bit word at address offset 0x2000 is checked. if the values do not match 0xa55a, the eeprom contents are ignored and the default values loaded. more information is provided in ?host interface registers? on page 82 . 2.1.1 eeprom auto-sizing mechanism the first procedure after reset is to read the offset address 0x2000 to check for the content 0xa55a. the eeprom physical presence, programmed state, and size are determined automatically. if the offset address 0x2000 contents do not match the 0xa55a value for any supported eeprom sizes, the AR9223 assumes the eeprom is not present on the pcb, or is present but not programmed. in either case, the logic uses the default values as described in ?serial eeprom interface? . 2.1.2 eeprom read/write protection mechanism the eeprom contains a 16-bit word protect mask value at address location 0x2010h that prevents software from accessing certain regions. the mask is 16 bits wide and contains eight sub-masks that are 2 bits wide. the sub-mask can have four values that determine the access types permitted to the associated protection region: 00: read/write access allowed 01: write-only access allowed 10: read-only access allowed 11: no access allowed 2.2 reset the rst_l pin controls the AR9223 chip reset. the AR9223 host interface receives two reset signals as below: rst_l pin controls the AR9223 power reset pci_rst_l controls the pci core reset in addition, the rtc_reset register provides software control of warm reset for the mac/ baseband and pcu blocks. see the register ?rtc reset and force sleep and force wakeup (rtc_reset)? on page 92 . 2.3 gpio the AR9223 provides nine configurable bi- directional general purpose i/o ports. each gpio can be independently configured as input or output using the gpio control register. information presented at the gpio inputs and outputs can be read from the register h_gpio_in_out (see ?gpio input and output (h_gpio_in_out)? on page 86 ). 2.4 led the AR9223 provides gpio pins to configure for led output. control for led output is provided by the mac_led register. 2.5 pci host interface this section provides a summary of the AR9223 pci interface. this interface is compatible with pci 2.3 standards and functions as the host interface for the AR9223, providing data and command transfer between the host software, the mac, and the configuration registers. for details, refer to the pci 2.3 standards specifications. do not copy free datasheet http://www.datasheet-pdf.com/
atheros communications, inc. AR9223 single-chip 2x2 mimo mac/bb/radio for 802.11n wlans ? 15 company confidential october 2009 ? 15 2.5.1 pci registers at system boot, the host uses the pci configuration registers to detect the type of device present and to perform low level pci configuration (e.g., assigning a base address to the device). an external serial eeprom provides device configuration information. at reset, some pci configuration registers load from the off-chip serial eeprom, whereas the host must program the others. conf iguration, control, and status registers for the various functional blocks of the AR9223 map to the memory space of the pci interface and thus can be accessed by the host. 2.6 signal description the AR9223 pci interface pins are described in ?signal-to-pin relationships and descriptions? on page 8 . table 2-2 shows the interface pins grouped by functional type. 2.7 host interface unit interrupts the AR9223 host interface unit supports: asynchronous mode interrupt synchronous mode interrupt table 6-11 on page 84 describes interrupt signals from various di fferent blocks on the AR9223. the signal/bits are the same for asynchronous and synchronous interrupts. software can control and program both the ?synchronous interrupt cause (h_intr_sync_caus)? and the ?asynchronous interrupt enable (h_intr_asyn_enab)? registers. because both registers contain similar bits, software should keep the synchronous and asynchronous interrupt enable registers mutually exclusive. table 2-2. types of pci interface signals type pin address and data pci_ad[31:0] pci_cbe[3:0]_l pci_par system pci_rst_l pci_clk pci_clkrun_l interface control pci_idsel pci_devsel_l pci_frame_l pci_irdy_l pci_stop_l pci_trdy_l arbitration pci_gnt_l pci_req_l interrupt pci_int_l pci error reporting pci_serr_l pci_perr_l power management pci_pme_l mode selection pci_mode do not copy free datasheet http://www.datasheet-pdf.com/
16 ? AR9223 single-chip 2x2 mimo mac/bb/radio for 802.11n wlans atheros communications, inc. 16 ? october 2009 company confidential do not copy free datasheet http://www.datasheet-pdf.com/
atheros communications, inc. AR9223 single-chip 2x2 mimo mac/bb/radio for 802.11n wlans ? 17 company confidential october 2009 ? 17 3. medium access control (mac) the mac consists of the following major functional blocks: 10 queue control units (qcus), 10 distributed coordination function (dcf) control units (dcus), a single dma rx unit (dru), and a single protocol control unit (pcu). see figure 3-1 . 3.1 overview the mac block supports full bus-mastering descriptor-based scatter/gather dma. frame transmission begins with the qcus. qcus manage the dma of frame data from the host through the pci interface, and determine when a frame is available for transmission. each qcu targets exactly one dcu. ready frames are passed from a qcu to its targeted dcu. the dcu manages the enhanced distributed coordinati on function (edcf) channel access procedure on behalf of the qcus associated with it. functionality of the mac block includes: tx frame data transfer from the host to the radio block using the pci bus rx frame data transfer from the radio block to host using the pci bus register access to all AR9223 registers interrupt generation and reporting sleep-mode (power-down) sequencing miscellaneous error and status reporting functions once the dcu gains access to the channel, it passes the frame to the pcu, which encrypts the frame and sends it to the baseband logic. the pcu handles both processing responses to the transmitted frame, and reporting the transmission attempt results to the dcu. frame reception begins in the pcu, which receives the incoming frame bitstream from the digital phy. the pcu decrypts the frame and passes it to the dru, which manages rx descriptors and writes the incoming frame data and status to the host memory through the pci interface. 3.2 descriptor the mac is responsible for transferring frames between the host memory (accessed using the pci interface) and the AR9223. for all normal frame transmit/receive activity, the host provides a series of descriptors to the mac, and the mac then parses the descriptors and performs the required set of data transfers. figure 3-1. mac block diagram do not copy free datasheet http://www.datasheet-pdf.com/
18 ? AR9223 single-chip 2x2 mimo mac/bb/radio for 802.11n wlans atheros communications, inc. 18 ? october 2009 company confidential 3.3 descriptor format the transmit (tx) descriptor format contains 24 32-bit words and the receive (rx) descriptor 13 32-bit words (see table 3-1 ). the first two words of the descriptor point to the next descriptor in th e linked list and to the data buffer associated with the descriptor. other words carry additional control information that affects how the mac processes the frame and its data. a descriptor is required to be aligned on a 32-bit boundary in host memory, although best performance is achieved if the descriptor is aligned on a cache-li ne boundary. the mac uses the final two words to report status information back to the host. see: table description table 3-1 dma descriptor format table 3-2 tx control descriptor format (words 2?13) table 3-3 tx status descriptors (words 14?23) table 3-4 rx control descriptor (words 2?3) table 3-5 rx status descriptor (words 4?12) table 3-1. dma descriptor format word bits field name description 0 31:0 link_ptr link pointer. contains the addres s of the next descriptor to be used; must be 32-bit aligned (bits [1:0] must be 0) 1 31:0 buf_ptr data buffer pointer. contains the starting address of the data buffer associated with this descriptor. a tx data buffer can begin at any byte address. a rx data buffer must be al igned on a 32-bit boundary in host memory, although best performance is achieved if the rx data buffer is cache-line aligned. (cache-line size varies from system to system.) 2?13 (tx) 2?3 (rx) 31:0 host-to- dma engine control information additional control information is pa ssed from host to dma engine. the format of these words varies dependin g on whether the descriptor is being used to tx a frame from host to pcu, or rx a frame from pcu to host. (see table 3-2 on page 19 , and table 3-4 on page 28 for details.) 14?23 (tx) 4?12 (rx) 31:0 dma completion status information status information reported by the dma engine when it has finished processing a descriptor. as with the control information, the format of the status information differs between tx and rx descriptors. (see table 3-3 on page 25 , and table 3-5 on page 28 for details.) do not copy free datasheet http://www.datasheet-pdf.com/
atheros communications, inc. AR9223 single-chip 2x2 mimo mac/bb/radio for 802.11n wlans ? 19 company confidential october 2009 ? 19 the tx descriptor format for words 2 through 13 is described in table 3-2 . table 3-2. tx control descriptor format (words 2?13) word bits field name description 2 11:0 frame_length frame length specifies the length, in bytes, of the entire mac frame, including the frame check sequence (fcs), initialization ve ctor (iv), and integrity check value (icv) fields. 12 vmf virtual more fragment if this bit is set, bursting is enabled for this frame. if no burst is in progress, it initiates a cts-protected burst if cts_enable is set. if a previous burst is in progress, it ignores the cts_enable bi t and assumes the burst is protected. 13 res reserved 14 low_rx_chain when set to 1, indicates that th e rx chain mask switches to low power mode after transmitting this frame. 15 clear_retry setting this bit di sables the retry bit from bein g set in the tx header on a frame retry (applies to both aggregate and non-aggregate frames). 21:16 tpc_0 tx power control for series 0 these bits pass unchanged to the baseband, where they are used to control the transmit power for the frame. 22 rts_enable request to send (rts) enable. at most, one of the ?rts_enable? and ?cts_enable? bits may be set; it is illegal to set both. set pcu transmits the frame using the rts/cts protocol clear pcu transmits the frame usin g the contention/backoff protocol 23 veol virtual end-of-list flag when set, indicates that the qcu should act as though th e descriptor had a null linkptr, even if the linkptr is not null. must be valid in the final descriptor of a frame and must be clear for all other descriptors of the frame. 24 clear_dest_mask clear destination mask bit flag if set, instructs the pcu and dcu to cl ear the destination mask bit at the index specified by the destidx field. 28:25 res reserved 29 int_req interrupt request flag set to one by the driver to request that the dma engine generate an interrupt upon completion of the frame to which this descriptor belongs. note that this field must be valid an d identical for all descriptors of the frame; that is, all descriptors for the frame must have this flag set, or all descriptors for the frame must have this flag clear. 30 dest_index_valid destination index valid flag specifies whether the contents of the destidx field are valid. 31 cts_enable proceed frame with cts flag if set, the pcu first sends a cts befo re sending the frame described by the descriptor. used for 802.11g and atheros xr frames to quiet legacy stations before sending a frame the legacy stations cannot interpret (even at the phy level). at most, one of the ?rts_enable? and ?cts_enable? bits may be set; it is illegal to set both bits. do not copy free datasheet http://www.datasheet-pdf.com/
20 ? AR9223 single-chip 2x2 mimo mac/bb/radio for 802.11n wlans atheros communications, inc. 20 ? october 2009 company confidential 3 11:0 buf_len data buffer length specifies the length, in bytes, of th e data buffer associated with this descriptor. tx data buffers may be any non-zero length buffers. this field must be valid for all descriptors. 12 more more descriptors in this frame flag set to one by the driver to indicate ad ditional descriptors (dma fragments) exist in the current frame. this field must be valid for all descriptors. 0 no more descriptors for the current frame 1 the current frame is continued in the next descriptor 19:13 dest_index destination table index specifies an index to an on-chip table of per-destination information. the pcu fetches the encryption key from the specified index in this table and uses the key to encrypt the frame. dma lo gic uses the index to maintain per- destination tx filtering status and other related information. 23:20 frame_type fram e type indication indicates to the pcu what type of fr ame is being sent. supported values: 0 normal frame 1 announcement traffic indica tion message (atim) frame 2 ps poll frame 3beacon 4probe response frame 15:5 reserved 24 no_ack no ack flag must be set for any frame that has th e 802.11 noack bit set in the qos field and for all other frame types (e.g., beacons) that do not receive acks. 1 do not wait for ack 28:25 res reserved 29 more_agg indicates aggregate boundaries 30 is_agg set for all descriptors for an aggregate 31 more_rifs more rifs burst flag when set, indicates that the current pa cket is not the last packet of an aggregate. all descriptors for all pa ckets of a rifs burst except the descriptors of the last packet must have th is bit set. all desc riptors of the last packet of a rifs burst must have this bit clear. table 3-2. tx control descriptor format (words 2?13) (continued) word bits field name description do not copy free datasheet http://www.datasheet-pdf.com/
atheros communications, inc. AR9223 single-chip 2x2 mimo mac/bb/radio for 802.11n wlans ? 21 company confidential october 2009 ? 21 4 14:0 burst_duration burst duration value (in s) if this frame is not part of a burst or th e last frame in a burs t, the value should be zero. in a burst, the value is the amou nt of time to reserve (via nav) after completing the current tx packet sequence (after the ack if applicable). 15 dur_update_en frame duration update control if set, the mac updates (overwrites) the duration field in the frame based on the current tx rate. if clear, the mac does not alter the contents of the frame?s duration field. note that the mac changes only the fr ame?s duration field. it does not alter the duration field in the rts/cts that precedes the frame itself if ?rts_enable? or ?cts_enable? is set. 19:16 tx_tries0 number of frame data exchange attempts permitted for tx series 0 a ?frame data exchange attempt? mean s a transmission at tempt in which the actual frame is sent on the air (in cont rast to the case in which the frame has rts enabled and the rts fails to receive a cts). in this case, the actual frame is not sent on the air, so this does n ot count as a frame data exchange attempt. a value of zero is illegal for the txdatatries0 field. 23:20 tx_tries1 number of frame data exchange a ttempts permitted for tr ansmission series 1. a value of zero means skip this transmission series. 27:24 tx_tries2 number of frame data exchange a ttempts permitted for tr ansmission series 2. a value of zero means skip this transmission series. 31:28 tx_tries3 number of frame data exchange a ttempts permitted for tr ansmission series 3. a value of zero means skip this transmission series. table 3-2. tx control descriptor format (words 2?13) (continued) word bits field name description do not copy free datasheet http://www.datasheet-pdf.com/
22 ? AR9223 single-chip 2x2 mimo mac/bb/radio for 802.11n wlans atheros communications, inc. 22 ? october 2009 company confidential 5 7:0 tx_rate0 tx rate for transmission series 0. 15:8 tx_rate1 tx rate for transmission series 1. see the rate table in ?tx_rate0? . 23:16 tx_rate2 tx rate for transmission series 2. see the rate table in ?tx_rate0? . 31:24 tx_rate3 tx rate for transmission series 3. see the rate table in ?tx_rate0? . 6 14:0 packet_duration0 packet duration 0 (in s) duration of the actual tx frame associated with txra te0. this time does not include rts, cts, ack, or any associated sifs. 15 rts_cts_qual0 qualifies ?rts_enable? or ?cts_enable? in the tx descriptor for tx series 0. 1 default behavior with respect to ?rts_enable? and ?cts_enable? 30:16 packet_duration1 packet duration 1 (in s) duration of the actual tx frame associated with txra te1. this time does not include rts, cts, ack, or any associated sifs. 31 rts_cts_qual1 qualifies ?rts_enable? or ?cts_enable? in the tx descriptor for tx series 1. 1 default behavior with respect to ?rts_enable? and ?cts_enable? table 3-2. tx control descriptor format (words 2?13) (continued) word bits field name description value desc value desc 0x1?0x7 res 0x18 cck_11mb_l 0x8 ofdm_48mb 0x19 cck_5_5mb_l 0x9 ofdm_24mb 0x1a cck_2mb_l 0xa ofdm_12mb 0x1b cck_1mb_l 0xb ofdm_6mb 0x1c cck_11mb_s 0xc ofdm_54mb 0x1d cck_5_5mb_s 0xd ofdm_36mb 0x1e cck_2mb_s 0xe ofdm_18mb 0xf ofdm_9mb value [1] [1]all values that are not listed here are reserved. note that for the short guard interval (gi = 1), ht20 mode is not allowed. desc stream ht20 gi = 0 (mbps) ht40 gi = 0 (mbps) ht40 gi = 1 (mbps) 0x80 mcs 0 1 6.5 13.5 15 0x81 mcs 1 1 13 27 30 0x82 mcs 2 1 19.5 40.5 45 0x83 mcs 3 1 36 54 60 0x84 mcs 4 1 39 81 90 0x85 mcs 5 1 52 108 120 0x86 mcs 6 1 58.5 121.5 135 0x87 mcs 7 1 65 135 150 0x88 mcs 8 2 13 27 30 0x89 mcs 9 2 26 54 60 0x8a mcs 10 2 39 81 90 0x8b mcs 11 2 52 108 120 0x8c mcs 12 2 78 162 180 0x8d mcs 13 2 104 216 240 0x8e mcs 14 2 117 243 270 0x8f mcs 15 2 130 270 300 do not copy free datasheet http://www.datasheet-pdf.com/
atheros communications, inc. AR9223 single-chip 2x2 mimo mac/bb/radio for 802.11n wlans ? 23 company confidential october 2009 ? 23 7 14:0 packet_duration2 packet duration 2 (in s) duration of the actual tx frame associated with txra te2. this time does not include rts, cts, ack, or any associated sifs. 15 rts_cts_qual2 qualifies ?rts_enable? or ?cts_enable? in the tx descriptor for tx series 2. 1 default behavior with respect to ?rts_enable? and ?cts_enable? 30:16 packet_duration3 packet duration 3 (in s) duration of the actual tx frame associated with txra te3. this time does not include rts, cts, ack, or any associated sifs. 31 rts_cts_qual3 qualifies ?rts_enable? or ?cts_enable? in the tx descriptor for tx series 3. 1 default behavior with respect to ?rts_enable? and ?cts_enable? 8 15:0 agg_length aggregate length 17:16 res reserved 25:18 pad_delim number of delimiters to add at th e end of a packet. the encryption field must be valid for all descriptions. 28:26 encrypt_type encryption type 0 none 0 pad bytes 1 wep 4 pad bytes 2 aes 8 pad bytes 3 tkip 12 pad bytes 31:29 res reserved 9 0 20_40_0 20_40 control for tx series 0 0 ht20 tx packet 1 ht40 tx packet 1 gi_0 guard interval control for tx series 0 0 normal guard interval 1 short guard interval 4:2 chain_sel_0 chain select fo r tx series 0. 1, 2, and 3 are the only valid values. bit [0] chain 0 is active bit [1] chain 1 is active bit [2] reserved 5 20_40_1 20_40 control for tx series 1 0 ht20 tx packet 1 ht40 tx packet 6 gi_1 guard interval control for tx series 1 0 normal guard interval 1 short guard interval 9:7 chain_sel_1 chain select fo r tx series 1. 1, 2, and 3 are the only valid values. bit [0] chain 0 is active bit [1] chain 1 is active bit [2] reserved 10 20_40_2 20_40 control for tx series 2 0 ht20 tx packet 1 ht40 tx packet table 3-2. tx control descriptor format (words 2?13) (continued) word bits field name description do not copy free datasheet http://www.datasheet-pdf.com/
24 ? AR9223 single-chip 2x2 mimo mac/bb/radio for 802.11n wlans atheros communications, inc. 24 ? october 2009 company confidential 9 (cont.) 11 gi_2 guard interval control for tx series 2 0 normal guard interval 1 short guard interval 14:12 chain_sel_2 chain select for tx series 2. 1, 2, and 3 are th e only valid values. bit [0] chain 0 is active bit [1] chain 1 is active bit [2] reserved 15 20_40_3 20_40 control for tx series 3 0 ht20 tx packet 1 ht40 tx packet 16 gi_3 guard interval control for tx series 3 0 normal guard interval 1 short guard interval 19:17 chain_sel_3 chain select for tx series 3. 1, 2, and 3 are th e only valid values. bit [0] chain 0 is active bit [1] chain 1 is active bit [2] reserved 27:20 rts_cts_rate rts or se lf-cts rate selection specifies the rate at which the rts will send if ?rts_enable? is set, or at which self cts will send if cts_enable is set. see the rate table in ?tx_rate0? . 31:28 stbc the stbc settings for all four series if bit 0 is set, stbc is enabled for tx series 0, etc. only the lower bit of the two-bit stbc will be set because stbc is only supported for single stream. 10 23:0 antenna_0 antenna switch for tx series 0 31:24 res reserved 11 23:0 antenna_1 antenna switch for tx series 1 29:24 tpc_1 tx power control (tpc) for tx series 1 these bits pass unchanged to the baseband to control tx power for the frame. 31:30 res reserved 12 23:0 antenna_2 antenna switch for tx series 2 29:24 tpc_2 tx power control (tpc) for tx series 2 these bits pass unchanged to the baseband to control tx power for the frame. 31:30 res reserved 13 23:0 antenna_3 antenna switch for tx series 3 29:24 tpc_3 tx power control (tpc) for tx series 3 these bits pass unchanged to the baseband to control tx power for the frame. 31:30 res reserved table 3-2. tx control descriptor format (words 2?13) (continued) word bits field name description do not copy free datasheet http://www.datasheet-pdf.com/
atheros communications, inc. AR9223 single-chip 2x2 mimo mac/bb/radio for 802.11n wlans ? 25 company confidential october 2009 ? 25 the tx descriptor format for words 14 through 24 is described in table 3-3 . table 3-3. tx status descriptor format (words 14?23) word bits field name description 14 7:0 rssi_ant00 rx ack signal strength indicator of control channel chain 0. a value of 0x80 (?128) indicates an invalid number. 15:8 rssi_ant01 rx ack signal strength indicator of control channel chain 1. a value of 0x80 (?128) indicates an invalid number. 23:16 res reserved 29:24 res reserved 30 ba_status block ack status if set this bit indicates that the ba_bitmap values are valid. 31 res reserved 15 0 frm_xmit_ok frame tr ansmission success set the frame was transmitted successfully clear no ack or ba was received during frame transmission 1 excessive_retries excessive tries if set, transmission of the frame fa iled because the try limit was reached before the frame was transmitted succ essfully. valid only for the final descriptor of a frame, and only if ?frm_xmit_ok? is clear. 2 fifo_underrun tx fifo underrun flag if set, frame tran smission failed because the dma engine was not able to supply the pcu with data as quickly as the baseband was requesting data. valid only for non-aggreg ate or non-rifs underrun conditions unless the underrun occurred on the first packet of the aggregate or rifs burst. see also the description for ?tx_dlmtr_ underrun_err? and ?tx_data_ underrun_err? . valid only if ?frm_xmit_ok? is clear. 3 filtered frame transmission filter indication if set, indicates that frame was not transmitted because the corresponding destination mask bit was set when the frame reached the pcu, or the frame violated txop on the first pa cket of a burst. valid if ?frm_xmit_ok? is clear. 7:4 rts_fail_cnt rts failure count reports the number of times an rts was sent but no cts was received for the final transmissi on series (see ?final_tx_index? ). for frames with ?rts_enable? clear, this count is always zero . note that this count increments only when the rts/cts exchange fails. in particular, this count does not increment if the rts/cts exchange succeeds but the frame itself fails because no ack was received. valid only for the final descriptor of a frame, regardless of the state of ?frm_xmit_ok? . 11:8 data_fail_cnt data failure count reports the number of times the actu al frame (as opposed to the rts) was sent but no ack was received for th e final transmission series (see ?final_tx_index? ). valid only for the final descri ptor of a frame, regardless of the state of ?frm_xmit_ok? . 15:12 virtual_retry_cnt virtual collision count reports the number of virtual collisions that occurred before transmission of the frame ended. the counter value saturates at 0xf. a virtual collision refers to the case, as described in the 802.11e qos specification, in which two or more output queues contend for a txop simultaneously. in such cases, all lower-priority output queues experi ence a ?virtual collision? in which the frame is treated as if it had been sent on the air but failed to receive an ack. 16 tx_dlmtr_ underrun_err tx delimiter underrun error this error only occurs on aggregate frames when the underrun conditions happens while the mac is send ing delimiters. do not copy free datasheet http://www.datasheet-pdf.com/
26 ? AR9223 single-chip 2x2 mimo mac/bb/radio for 802.11n wlans atheros communications, inc. 26 ? october 2009 company confidential 15 (cont.) 17 tx_data_ underrun_err tx data underrun error. this error only occurs on aggregate frames when the underrun condition happens while the mac is sending the data portion of the frame or delimiters. 18 desc_config_error descriptor configuration error. this error occurs if the current 20_40 values are not among the four valid combinations, or if ?tx_dlmtr_ underrun_err? or ?tx_data_ underrun_err? are set. 19 tx_timer_expired tx timer expired. this bit is set when the tx frame takes longer to send to the baseband than is allowed based on the tx_timer register. some regulatory domains require that tx packets may not exceed a certain amount of transmit time. 31:20 res reserved 16 31:0 send_timestamp timestamp at the start of transmit. a snapshot of the lower 32 bits of pc u's timestamp (tsf value). this field can aid the software driver in implem enting requirements associated with the amaxtransmitmsdulifetime mac attribute. the tx timestamp is sampled upon tx_fra me signal rising that goes from the mac to the baseband. this value corresponds to the last attempt at packet transmission (not the first attempt). 17 31:0 ba_bitmap_0-31 block ack bitmap 0 to 31. the values from the block that ack re ceived after successful transmission of an aggregate frame. bit 0 if set re presents the successful reception of the packet with the sequence number matching the seq_num value. 18 31:0 ba_bitmap_32-63 block ack bitmap 32 to 63. the values from the block that ack re ceived after successful transmission of an aggregate frame. bit 0 if set re presents the successful reception of the packet with the sequence number matching seq_num + 32. 19 7:0 rssi_ant10 receive ack signal strength indicator of extension channel chain 0. a value of 0x80 (?128) indicates an invalid number. 15:8 rssi_ant11 receive ack signal strength indicator of extension channel chain 1. a value of 0x80 (?128) indicates an invalid number. 23:16 res reserved 31:24 ack_rssi_combined receive ack signal strength in dicator of combination of all active chains on the control and extension channels. the value of 0x80 (?128) is used to indicate an invalid number. 20 31:0 evm error vector magnitude 0. evm is not calculated for legacy frames so this value should always be 0x80 because ack/ba should be sent at legacy rates. 21 31:0 evm error vector magnitude 1. evm is not calculated for legacy frames so this value should always be 0x80 because ack/ba should be sent at legacy rates. 22 31:0 evm error vector magnitude 2. evm is not calculated for legacy frames so this value should always be 0x80 because ack/ba should be sent at legacy rates. table 3-3. tx status descriptor format (words 14?23) (continued) word bits field name description do not copy free datasheet http://www.datasheet-pdf.com/
atheros communications, inc. AR9223 single-chip 2x2 mimo mac/bb/radio for 802.11n wlans ? 27 company confidential october 2009 ? 27 23 0 done descriptor completion flag. set to one by the dma engine when it has finished processing the descriptor and has updated the status information. valid only for the final descriptor of a frame, re gardless of the state of ?frm_xmit_ok? . the driver is responsible for tracking what descriptors are associated with a frame. when the dma engine sets the done flag in the final descriptor of a frame, the driver must be able to de termine what other descriptors belong to the same frame and thus also have been consumed. 12:1 seqnum tx sequence number. indicates the sequence number from the response block ack. this field should only be consulted if the tx frame was an aggregate. because hardware does not update the sequence number, this field does not need to be consulted for non-aggregate fram es. for aggregates, this sequence number may not be the sequence numb er of the first tx frame of the aggregate. more than likely has an ol der sequence number if the hardware of the other side keeps track of prio r sequence numbers. it may sometimes have a newer sequence number if the first packet of the aggregate failed. 16:13 res reserved 17 txop_exceeded txop has been exceeded. indicates that this tx frame had to be filtered because the amount of time to transmit this packet sequence would exceed the txop li mit (which should only occur when software progra ms the txop limit improperly). 20:18 res reserved 22:21 final_tx_index final transm ission attempt series index. specifies the number of the tx series that caused fram e transmission to terminate. 24:23 res reserved 25 pwr_mgmt power management state. indicates the value of the power manage ment bit in the frame control field of the response ack frame. 27:26 res reserved 31:28 tid traffic indentifier of block ack. this field indicates the tid of the resp onse block ack. th is field is only valid on the last descriptor of the last packet of an aggregate. table 3-3. tx status descriptor format (words 14?23) (continued) word bits field name description do not copy free datasheet http://www.datasheet-pdf.com/
28 ? AR9223 single-chip 2x2 mimo mac/bb/radio for 802.11n wlans atheros communications, inc. 28 ? october 2009 company confidential the dma rx logic (the dru block) manages rx descriptors and transfers the incoming frame data and status to the host through the pci interface. the rx descriptor format for words 2 and 3 is described in table 3-4 . the rx descriptor format for words 4 through 13 is described in table 3-5 . table 3-4. rx control descriptor format (words 2?3) word bits field name description 2 31:0 res reserved 3 11:0 buf_len data buffer length (in bytes). specifies the length of the data buffer as sociated with this descriptor. rx data buffers must have a length that is an integral multiple of four bytes. 12 res reserved 13 int_req interrupt request flag. indicates whether the dma engine should generate an interrupt upon frame completion. 0 do not generate an interreq interrupt upon frame completion 1 generate an interreq interrupt upon frame completion 31:14 res reserved table 3-5. rx status descriptor format (words 4?12) word bits field name description 4 7:0 rssi_ant00 receive signal strength indicator of control channel chain 0. a value of 0x80 (?128) indicates an invalid number. 15:8 rssi_ant01 receive signal strength indicator of control channel chain 1. a value of 0x80 (?128) indicates an invalid number. 23:16 res reserved 31:24 rx_rate rx rate indication. indicates the rate at which this frame transmits from the source. encodings match those used for the tx_rate_* field in word 5 of the tx descriptor. valid only if ?frame_rx_ok? is set, or if it is clear and the ?phy_error? flag is clear. 5 11:0 data_len received data length specifies the length, in bytes, of the data actually received into the data buffer associated with this descri ptor. the actual received data length is between zero and the total size of the data buffer, as sp ecified originally in this field (see the description for ?buf_len? ). valid for all descriptors. 12 more more descriptors in this frame flag if set, then this is not the final descriptor of the frame. if clear, this descriptor is the final one of the frame. valid for all descriptors. 0 no more descriptors for the current frame 1 the current frame is continued in the next descriptor 13 res reserved 21:14 num_delim number of zero length pad delimiters after current packet this field does not include the start deli miter required between each packet in an aggregate. this field is only valid for aggregate packets except for the last packet of an aggregate 31:22 res reserved do not copy free datasheet http://www.datasheet-pdf.com/
atheros communications, inc. AR9223 single-chip 2x2 mimo mac/bb/radio for 802.11n wlans ? 29 company confidential october 2009 ? 29 6 31:0 rcv_timestamp a snapshot of the pc u's timestamp (tsf value) (in ms) bits [31:0] of the pcu's 64-bit tsf. in tended for packet logging and packet sniffing. the timestamp is sampled on th e rising edge of rx_clear, which goes from the baseband to the mac. 7 0 gi rx packet guard interval. if this value is clear, the rx frame used a long guard interval. if this value is set, the receive frame used a short guard interval. 1 20_40 rx packet 20 or 40 mhz bandwidth indicator. if this value is clear, the rx frame was a ht20 packet (20 mhz bandwidth). if this value is set, then the receive frame was a ht40 packet (40 mhz bandwidth). 2 duplicate rx packet duplicate indicator. if this value is set, the baseband has de termined that this pa cket is a duplicate packet. 7:3 res reserved 31:8 rx_antenna rx antenna value 8 7:0 rssi_ant10 receive signal strength indicator of control channel chain 0. a value of 0x80 (?128) indicates an invalid number. 15:8 rssi_ant11 receive signal strength indicator of control channel chain 1. a value of 0x80 (?128) indicates an invalid number. 23:16 res reserved 31:24 rssi_combined rx signal strength indicator of combination of al l active chains on the control and extension channels. the value of 0x80 (-128) is used to indicate an invalid number. 9 31:0 evm rx packet error vector magnitude 0. 10 31:0 evm rx packet error vector magnitude 1. 11 31:0 evm rx packet error vector magnitude 2. 12 0 done descriptor completion flag set to one by the dma engine when it has finished processi ng the descriptor and has updated the status information.valid for all descriptors. 0 the mac has not finished processing the descriptor. valid only for the final descriptor of a frame 1 the mac has finished processing the descriptor and has updated the status information 1 frame_rx_ok frame reception success flag if set, the frame was received successfully. if clear, an error occurred during frame reception. 0 an error occurred during frame reception 1 frame received successfully 2 crc_error cyclic redundancy code (crc) error flag valid only for the final descriptor of a frame, and only if the ?frame_rx_ok? flag is clear. 0 frame received without a crc error 1 reception of frame failed because of an incorrect crc value 3 decrypt_crc_err decryption crc failure flag. valid only for the final descriptor of a frame, and only if the frmrcvok flag is clear. table 3-5. rx status descriptor format (words 4?12) (continued) word bits field name description do not copy free datasheet http://www.datasheet-pdf.com/
30 ? AR9223 single-chip 2x2 mimo mac/bb/radio for 802.11n wlans atheros communications, inc. 30 ? october 2009 company confidential 12 (cont.) 4 phy_error phy error flag. if set, then reception of the frame failed because the phy encountered an error. in this case, bits [15:8] of this word in dicate the specific type of phy error; see the baseband specification for details. valid only if the 'frame_rx_ok' flag is clear. 5 mic_error michael integrity check error flag. if set, then the frame?s tkip michae l integrity check value did not verify correctly. valid only when all of the following are true: the ?frame_rx_ok? bit is clear the frame was decrypted using tkip the frame is not a fragment 6 pre_delim_crc _err delimiter crc error detected before this current frame 7resreserved 8 key_idx_valid if ?frame_rx_ok? is set, then this field cont ains the decryption key table index valid flag. if set, indicates th at the pcu successfully located the frame?s source address in its on-chip key table and that the keyidx field reflects the table index at which the de stination address was found. if clear, indicates that the pcu failed to loca te the destination address in the key table and that the contents of keyidx field are undefined. if ?frame_rx_ok? is clear and the ?phy_error? bit is set, then this field contains bit [0] of the phy error code. in both cases, this field is valid only for the final descriptor of a frame. 15:9 key_idx if ?frame_rx_ok? is set, then this field cont ains the decryption key table index valid flag. if set, indicates th at the pcu successfully located the frame?s source address in its on-chip key table and that the keyidx field reflects the table index at which the de stination address was found. if clear, indicates that the pcu failed to loca te the destination address in the key table and that the contents of keyidx field are undefined. if ?frame_rx_ok? is clear and the ?phy_error? bit is set, then this field contains bits [4:1] of the phy error code, the upper three bits are zero. in both cases, this field is valid on ly for the final descriptor of a frame. 16 more_agg more aggregate flag. this bit is only set for the last descript or of the last packet of an aggregate. 17 aggregate aggregate flag. if set indicates that this packet is part of an aggregate. 18 post_delim_crc_ err delimiter crc error detected after this current frame. only occurs when the start delimiter of the last frame in an aggregate is bad. 29:19 res reserved 30 decrypt_busy _err decrypt busy error. if set it indicates new frame arrived before decryption completed for the previous frame. 31 key_miss key cache miss indication. if set, indicates that the pcu could n ot locate a valid description key for the frame. valid only if the ?frame_rx_ok? is clear. table 3-5. rx status descriptor format (words 4?12) (continued) word bits field name description do not copy free datasheet http://www.datasheet-pdf.com/
atheros communications, inc. AR9223 single-chip 2x2 mimo mac/bb/radio for 802.11n wlans ? 31 company confidential october 2009 ? 31 3.4 queue control unit (qcu) the queue control unit performs two tasks: managing the tx descriptor chain processing for frames pushed to the qcu from the host by traversing the linked list of tx descriptors and transferring frame data from the host to the targeted dcu. managing the queue tx policy to determine when the frame at the head of the queue should be marked as available to transmit. the mac contains ten qc us, each with all the logic and state registers needed to manage a single queue (linked list) of tx descriptors. a qcu is associated with exactly one dcu. when a qcu prepares a new frame, it signals ready to the dcu. when the dcu accepts the frame, the qcu responds by getting the frame data and passing it to the dcu for eventual transmission to the pcu and on to the air. the host controls how the qcu performs these tasks by writing to various qcu configuration registers (see ?qcu registers? on page 66 ). 3.4.1 dcf control unit (dcu) collectively, the ten dcus implement the edcf channel access arbitration mechanism defined in the task group e (tge) qos extension to the 802.11 specification. each dcu is associated with one of the eight edcf priority levels and arbitrates with the other dcus on behalf of all qcus associated with it. a central dcu arbiter moni tors the state of all dcus and grants one the next access to the pcu (that is, access to the channel). because the edcf standard defines eight priority levels, the first eight dcus (dcus 0?7) map directly to the eigh t edcf priority levels. the two additional dcus handle beacons and beacon-gated frames for a total of ten dcus. the mapping of physical dcus to absolute channel access priorities is fixed and cannot be altered by software: the highest-priority dcu is dcu 9. typically, this dcu is the one associated with beacons. the next highest priority dcu is dcu 8. typically, this dcu is the one associated with beacon-gated frames. the remaining eight dcus priority levels are filled with dcus 7 through 0. among these 8 dcus, dcu 7 has highest priority, dcu 6 the next highest priority, and so on through dcu 0, which has the lowest priority. typically, these dcus are associated with edcf pr iorities seven through zero, respectively. 3.5 protocol control unit (pcu) the pcu is responsible for the details of sending a frame to the baseband logic for transmission, for receiving frames from the baseband logic and passing the frame data to the dru, including: buffering tx and rx frames encrypting and decrypting generating ack, rts, and cts frames maintaining the timing synchronization function (tsf) inserting and verifying fcs generating virtual clear channel assessment (cca) updating and parsing beacons the pcu is primarily responsible for buffering outgoing and incoming frames and conducting medium access compatible with the ieee 802.11 dcf protocol. figure 3-2 shows the pcu functional block diagram. figure 3-2. pcu functional block diagram do not copy free datasheet http://www.datasheet-pdf.com/
32 ? AR9223 single-chip 2x2 mimo mac/bb/radio for 802.11n wlans atheros communications, inc. 32 ? october 2009 company confidential do not copy free datasheet http://www.datasheet-pdf.com/
atheros communications, inc. AR9223 single-chip 2x2 mimo mac/bb/radio for 802.11n wlans ? 33 company confidential october 2009 ? 33 4. digital phy block the digital physical layer (phy) block is described in 802.11 draft-n mode and 802.11 a/b/g legacy mode. transmit and receive paths are provided and shown as block diagrams for 802.11 draft-n mode. 4.1 overview the digital phy block is a half-duplex, ofdm, cck, dsss baseband processor compatible with ieee 802.11n and 802.11b/g. the AR9223 supports phy data rates up to 300 mbps in 20- and 40-mhz channel modes and all data rates defined by the ieee 802.11b/g standard (1? 54 mbps). modulation schemes include bpsk, qpsk, 16-qam, 64-qam and forward error correction coding with rates of 1/2, 2/3, 3/4, 5/6. 4.2 802.11n (mimo) mode frames beginning with training symbols are used for signal detection, automatic gain control, frequency offset estimation, symbol timing, and channel esti mation. this process uses 56 sub-carriers for 20-mhz ht mode: 52 for data transmission and 4 for pilots. it uses 114 sub-carriers for 40-mhz ht mode: 108 for data transmission and 6 for pilots. 4.2.1 transmitter (tx) figure 4-1 shows the tx path digital phy 802.11n (mimo mode) block diagram. the pcu block initiates transmission. the digital phy powers on the digital to analog converter (dac) and tran smit portions of the AR9223. the training symbols are a fixed waveform and are generated within the digital phy in parallel with the pcu sending the tx header (frame length, data rate, etc.). the pcu must send transmitted data quickly enough to prevent buffers in the digital phy from becoming empty. the pcu is prevented from sending data too quickly by pauses generated within the digital phy. figure 4-1 shows a 2x2 mimo system with two spatial data streams. the spatial parser splits the coded data into multiple data streams by allocating the proper number of bits to each data stream so that the number of data symbols resulted in each stream is the same. then it interleaves coded bits across different data subcarriers followed by the modulation. to achieve the maximum spatial diversity, the walsh matrix can be used to orthogonally mix the two modulated streams before the streams undergo ifft processing to produce time domain signals. 4.2.2 receiver (rx) figure 4-2 shows the rx path digital phy 802.11n (mimo mode) block diagram. the receiver inverts the transmitter?s steps, performing a fast fourier transform (fft), extracting bits from rece ived constellations, de- interleaving, accounting for puncturing, decoding, and descrambling. the rx block shows 2x2 mimo configuration. figure 4-2 shows a frequency-domain equalizer handling degradation due to multi-path. figure 4-1. digital phy 802.11n tx state machine/scrambler encode puncture/pad spatial parser interleave interleave modulator modulator walsh matrix ifft ifft fir fir dac dac control data to pcu to radio block figure 4-2. digital phy 802.11n rx state machine/scrambler descrambler decoder spatial combiner de-interleaver mimo equalizer fft fft fir fir adc adc control data to pcu from radio block de-interleaver do not copy free datasheet http://www.datasheet-pdf.com/
34 ? AR9223 single-chip 2x2 mimo mac/bb/radio for 802.11n wlans atheros communications, inc. 34 ? october 2009 company confidential 4.3 802.11 a/b/g legacy mode 4.3.1 transmitter the AR9223 digital phy incorporates an ofdm and dsss transceiver that supports all data rates defined by ieee 802.11b/g. legacy mode is detected on per-frame basis. plcp frames are detected for legacy network information. the transmitter switches dynamically to generate legacy signals (802.11b/g). 4.3.2 receiver the receiver is capa ble of dynamically detecting legacy, ht 20 mhz or 40 mhz frames and will demodulate the frame according to the detected frame type. do not copy free datasheet http://www.datasheet-pdf.com/
atheros communications, inc. AR9223 single-chip 2x2 mimo mac/bb/radio for 802.11n wlans ? 35 company confidential october 2009 ? 35 5. radio block the transceiver of the AR9223 solution consists of these major functional blocks: 2 x receive chain each chain = radio + bb programmable gain filter 2 x transmit chain each chain = radio + bb programmable gain filter frequency synthesizer (synth) associated bias/control (bias) see figure 5-1 . 5.1 receiver (rx) block the receiver converts an rf signal (with 20 mhz or 40 mhz bandwidth) to baseband i and q outputs. the dual band receiver operates in the 2.4 ghz band to support cck and ofdm signals for 802.11b, 802.11g, and 802.11n. the 2.4 ghz receiver implements a direct conversion architecture. the receiver consists of a low noise amplifier (lna), in-phase (i) and quadrature (q) radio frequency mixers, and a baseband programmable gain amplifier (pga). the mixer converts the output of the on-chip lna to baseband i and q signals. the i and q signals are low-pass filt ered and amplified by a baseband programmable gain filter controlled by digital logic. the ba seband signals are sent to the adc within the mac/baseband processor. figure 5-1. radio functional block diagram do not copy free datasheet http://www.datasheet-pdf.com/
36 ? AR9223 single-chip 2x2 mimo mac/bb/radio for 802.11n wlans atheros communications, inc. 36 ? october 2009 company confidential the dc offset of the receive chain is reduced using multiple dacs controlled by the mac/ baseband processor. additionally, the receive chain can be digitally powered down to conserve power. 5.2 transmitter (tx) block the transmitter converts baseband i and q inputs to 2.4 ghz rf outputs as shown in figure 5-3 . the inputs to the transmitter are current outputs of the dac within the mac/ baseband processor. these currents are low- pass filtered through an on-chip reconstruction filter to remove spectral images and out-of- band quantization noise. the i and q signals are converted to rf signals using an integrated up-conversion architecture. the baseband i and q signals are up-converted directly to rf using a pair of quadrature mixers. these signals are driven off-chip through a power amplifier. the transmit chain can be digitally powered down to conserve power. to ensure that the fcc limits are observed and the output power stays close to the maximum allowed, the transmit output power is adjusted by a closed loop, digitally programmed, control loop at the start of each packet. the AR9223 provides a closed loop power control based on an off-chip power detector. figure 5-2. radio receive chain block diagram figure 5-3. radio transmit chain block diagram do not copy free datasheet http://www.datasheet-pdf.com/
atheros communications, inc. AR9223 single-chip 2x2 mimo mac/bb/radio for 802.11n wlans ? 37 company confidential october 2009 ? 37 5.3 synthesizer (synth) block the radio supports one on-chip synthesizer to generate local oscillator (lo) frequencies for the receiver and transmitter mixers. the synthesizer has the topology shown in figure 5-4 . the AR9223 generates the reference input from a 40 mhz crystal for the synthesizer. an on- chip voltage controlled oscillator (vco) provides the desired lo signal based on a phase/frequency locked loop. upon power up or channel reselection, the synthesizer takes approximately 0.2 ms to settle. 5.4 bias/control (bias) block the bias/control block provides the reference voltages and currents for all other circuit blocks (see figure 5-5 ). an on-chip bandgap reference circuit provides the needed voltage and current references based on an external 6.19 k 1% resistor. figure 5-4. radio synthesizer block diagram synthesizer phase frequency detector charge pump loop filter (on-chip) vco divider channel select to local oscillator reference input from mac/bb figure 5-5. bias/control block diagram bias reference resistor biasing control registers control interface from baseband ... do not copy free datasheet http://www.datasheet-pdf.com/
38 ? AR9223 single-chip 2x2 mimo mac/bb/radio for 802.11n wlans atheros communications, inc. 38 ? october 2009 company confidential do not copy free datasheet http://www.datasheet-pdf.com/
atheros communications, inc. AR9223 single-chip 2x2 mimo mac/bb/radio for 802.11n wlans ? 39 company confidential october 2009 ? 39 6. register descriptions 6.1 host pci configuration space registers table 6-1 summarizes the AR9223 host pci configuration space regi sters. these registers are accessed by the host using pci configure operations and are used at boot time by the host to detect the type of card present and to perform low-level configuration, such as assigning base addresses to the card. at reset, some of these registers are hard coded on the chip but new values can be loaded from an off-chip serial eeprom, while others must be programmed by the host or are initialized by the AR9223 hardware. refer to ?eeprom interface registers? on page 82 for register values that are loaded from the eeprom upon reset. registers that are loaded by the host or initialized by the AR9223 are identified in table 6-1 . refer to version 2.3 of the pci bus standard for detailed information on these registers. table 6-1. host pci configuration space registers offset name description initialized by page 0x00 vendor id identification of the manufacturer eeprom page 40 0x02 device id identification of the device type eeprom page 40 0x04 command controls accessibility of the device host page 40 0x06 status provides status of th e device?s functionality AR9223/ eeprom page 41 0x08 revision id identification of the device?s revision eeprom page 42 0x09 class code identification of the device?s basic function eeprom page 42 0x0c cache line size specifies system cache line size host page 42 0x0d latency timer defines the minimum time (in pci bus cycles) the bus master can retain ownership of the pci bus host page 42 0x0e header type defines device?s configuration header format eeprom page 43 0x10 base address base address for accessing the wlan memory mapped registers host page 43 0x2c subsystem vendor id id entification of the subsystem manufacturer eeprom page 43 0x2e subsystem id identification of the subsystem de vice type eeprom page 43 0x34 capabilities pointer pointer to th e device?s list of capabilities eeprom page 44 0x3c interrupt line defines whether the device?s interrupts are generated using the pci inte rrupt pins, or using the message-signaled interrupts (msi) capability host page 44 0x3d interrupt pin defines specific pc i interrupt pins associated with particular functions of the device eeprom page 44 0x3e mingnt indicates how long the device retains pci bus ownership eeprom page 44 0x3f maxlat indicates how often the device accesses the pci bus eeprom page 44 do not copy free datasheet http://www.datasheet-pdf.com/
40 ? AR9223 single-chip 2x2 mimo mac/bb/radio for 802.11n wlans atheros communications, inc. 40 ? october 2009 company confidential 6.1.1 vendor id offset: 0x00 access: read only size: 16 bits contains the vendor identification number. value of this register can be loaded from the eeprom when the eeprom is attached, or if the eeprom content is not valid, a value of 0x168c returns when read from the register. 6.1.2 device id offset: 0x02 access: read only size: 16 bits this register identifies the device type. value of this register can be loaded from the eeprom when the eeprom is attached, or if the eeprom content is not valid, a value of 0xff1d returns when read from the register. 6.1.3 command offset: 0x04 access: read/write size: 16 bits reset value: undefined this register provides access control of the AR9223 pci interface. the register is controlled by the host. bit name description 15:0 vendor_id vendor identification bit name description 15:0 device_id device identification bit name description 0 io_space i/o space 0 disable 1enable 1 mem_space memory space 2b u s _ m s t rb u s m a s t e r 3 spec_cycles special cycles 4 mem_wr_inv memory write and invalidate enable 5 vga_snoop vga palette snoop 6 par_err_resp parity error response 7 step_cntl stepping control 8 serr_en system error enable 9 fast_bb_en fast back-to-back enable 15:10 res reserved. must be written with zero. on read, can contain any value. do not copy free datasheet http://www.datasheet-pdf.com/
atheros communications, inc. AR9223 single-chip 2x2 mimo mac/bb/radio for 802.11n wlans ? 41 company confidential october 2009 ? 41 6.1.4 status offset: 0x06 access: read/write, except as noted size: 16 bits reset value: 0x0290 this register provides status of the functionality provided by the AR9223 pci interface. this register is mostly controlled by the AR9223. bit name description 3:0 res reserved. must be written with zero. on read, can contain any value. 4 cap_list capabilities list. read only. 5 66mhz_en 66 mhz capable. read only. 6 res reserved. must be written with zero. on read, can contain any value. 7 fast_bb fast back-to-back capable. read-only. 0 disabled 1enabled 8 md_par_err master data parity error on read: 0no error 1error on write: 0 do not clear bit 1 clear error bit 10:9 devsel_timing device select timing. read only. 01 medium 11 sig_targ_abort signaled target abort on read: 0 no abort 1abort on write: 0 do not clear bit 1 clear abort bit 12 rx_targ_abort received target abort 13 rx_mas_abort received master abort 14 sig_sys_err signaled system error on read: 0no error 1error on write: 0 do not clear bit 1 clear error bit 15 detect_par_err detected parity error do not copy free datasheet http://www.datasheet-pdf.com/
42 ? AR9223 single-chip 2x2 mimo mac/bb/radio for 802.11n wlans atheros communications, inc. 42 ? october 2009 company confidential 6.1.5 revision id offset: 0x08 access: read/write size: 8 bits this register contains the device revision identification number. value of this register can be loaded from the eeprom when the eeprom is attached, or if the eeprom content is not valid, a value of 0x1 returns when read from the register. 6.1.6 class code offset: 0x09 access: read only size: 24 bits this register contains the class code identification number th at identifies the basic function of the device. value of this register can be loaded from the eeprom when the eeprom is attached, or if the eeprom content is not valid, a value of 0x0d8000 returns when read from the register. 6.1.7 cache line size offset: 0x0c access: read/write size: 8 bits reset value: 0x00 this register contains the size of the system cache line. this register is controlled by the host. 6.1.8 latency timer offset: 0x0d access: read/write size: 8 bits reset value: 0x00 this register provides the minimum amount of time, in pci clock cycles , that the bus master can retain ownership of the bus whenever it initiates a new transaction. this register is controlled by the host. bit name description 7:0 revision_id revision identification bit name description 23:0 class_code class code identification value bit name description 7:0 cache_sz cache line size, in units of 32-bit words (4 bytes) bit name description 7:0 latency_tmr latency timer do not copy free datasheet http://www.datasheet-pdf.com/
atheros communications, inc. AR9223 single-chip 2x2 mimo mac/bb/radio for 802.11n wlans ? 43 company confidential october 2009 ? 43 6.1.9 header type offset: 0x0e access: read only size: 8 bits this register contains the header type information. value can be loaded from the eeprom. 6.1.10 base address offset: 0x10 access: bits [15:0] are read only (always return 0); bits [31:16} are read/write size: 32 bits reset value: undefined this register contains the base address for accessing the AR9223 wlan memory mapped registers. this register is controlled by the host. 6.1.11 subsystem vendor id offset: 0x2c access: read only size: 16 bits this register contains the subsystem vendor identification number. value of this register can be loaded from the eeprom when the eeprom is attached, or if the eeprom content is not valid, a value of 0x168c returns when read from the register. 6.1.12 subsystem id offset: 0x2e access: read only size: 16 bits this register contains the subsystem device identification number. value of this register can be loaded from the eeprom when the eeprom is attached, or if the eeprom content is not valid, a value of 0xee1c returns when read from the register. bit name description 7:0 hdr_type header type 0 nonbridge pci device bit name description 31:0 base_addr base address bit name description 15:0 ssys_vend_id subsystem vendor id bit name description 15:0 ssys_id subsystem id do not copy free datasheet http://www.datasheet-pdf.com/
44 ? AR9223 single-chip 2x2 mimo mac/bb/radio for 802.11n wlans atheros communications, inc. 44 ? october 2009 company confidential 6.1.13 capabilities pointer (cap_ptr) offset: 0x34 access: read only size: 8 bits reset value: 0x40 this register contains the value of the capabilities pointer. default value is provided by the AR9223. 6.1.14 interrupt line (int_line) offset: 0x3c access: read/write size: 8 bits reset value: 0x00 this register contains the host interrupt controller?s interrupt line value that the device?s interrupt pin is connected to. this register is controlled by the host. 6.1.15 interrupt pin (int_pin) offset: 0x3d access: read only size: 8 bits reset value: 0x01 this register defines which of the four pci interrupt request pins, a pci function is connected to. value can be loaded from the eeprom. 6.1.16 mingnt offset: 0x3e access: read only size: 8 bits reset value: 0x00 this register contains a value that indicates how long the device (bus-master) retains pci bus ownership. value can be loaded from the eeprom. 6.1.17 maxlat offset: 0x3f access: read only size: 8 bits reset value: 0x00 this register contains the maximum latency value. value can be loaded from the eeprom. bit name description 7:0 cap_ptr capabilities pointer value bit name description 7:0 int_line interrupt line value bit name description 7:0 int_pin interrupt pin value bit name description 7:0 min_gnt minimum grant value bit name description 7:0 max_lat maximum latency value do not copy free datasheet http://www.datasheet-pdf.com/
atheros communications, inc. AR9223 single-chip 2x2 mimo mac/bb/radio for 802.11n wlans ? 45 company confidential october 2009 ? 45 6.2 AR9223 internal register descriptions this section describes the AR9223 internal registers. 6.2.1 general dma and rx-related registers table 6-2 shows the mapping of the general dma and rx-related (mac interface) registers. offset type page 0x0000?0x00fc general dma and rx -related (mac interface) page 45 0x0800?0x0a40 qcu page 66 0x1000?0x12f0 dcu page 72 0x2000?0x3ffc eeprom interface page 82 0x4000?0x409c host interface page 82 0x7000?0x7ffc rtc interface page 92 0x8000?0x97fc mac pcu page 95 table 6-2. general dma and rx-related registers offset name description page 0x0008 cr command page 46 0x000c rxdp receive queue descriptor pointer page 46 0x0014 cfg configuration and status page 47 0x0020 mirt maximum interrupt rate threshold page 48 0x0024 ier interrupt global enable page 48 0x0028 timt transmit interrup t mitigation thresholds page 48 0x002c rimt receive interrupt mitigation thresholds page 49 0x0030 txcfg transmit configuration page 49 0x0034 rxcfg receive configuration page 50 0x0040 mibc mib control page 50 0x0044 tops timeout prescale page 50 0x0048 rxnf rx no frame page 51 0x004c txnf tx no frame page 51 0x0050 rfgto receive frame gap timeout page 51 0x0054 rfcnt receive frame count limit page 51 0x0064 gtt global transmit timeout page 52 0x0068 gttm global transmit timeout mode page 52 0x006c cst carrier sense timeout page 52 0x0080 isr_p primary interrupt status page 53 0x0084 isr_s0 secondary interrupt status 0 page 55 0x0088 isr_s1 secondary interrupt status 1 page 55 0x008c isr_s2 secondary interrupt status 2 page 56 0x0090 isr_s3 secondary interrupt status 3 page 56 0x0094 isr_s4 secondary interrupt status 4 page 57 do not copy free datasheet http://www.datasheet-pdf.com/
46 ? AR9223 single-chip 2x2 mimo mac/bb/radio for 802.11n wlans atheros communications, inc. 46 ? october 2009 company confidential 6.2.1.1 command (cr) offset: 0x0008 access: read/write cold reset: 0x0 warm reset: (same as cold reset) 6.2.1.2 rx queue descriptor pointer (rxdp) offset: 0x000c access: read/write cold reset: (undefined) warm reset: (unaffected) 0x0098 isr_s5 secondary interrupt status 5 page 57 0x00a0 imr_p primary interrupt mask page 58 0x00a4 imr_s0 secondary interrupt mask 0 page 59 0x00a8 imr_s1 secondary interrupt mask 1 page 59 0x00ac imr_s2 secondary interrupt mask 2 page 60 0x00b0 imr_s3 secondary interrupt mask 3 page 60 0x00b4 imr_s4 secondary interrupt mask 4 page 61 0x00b8 imr_s5 secondary interrupt mask 5 page 61 0x00c0 isr_p_rac primary interr upt status read-and-clear page 62 0x00c4 isr_s0_s secondar y interrupt status 0 (shadow copy) page 62 0x00c8 isr_s1_s second ary interrupt status 1 (shadow copy) page 62 0x00cc isr_s2_s second ary interrupt status 2 (shadow copy) page 62 0x00d0 isr_s3_s secondar y interrupt status 3 (shadow copy) page 63 0x00d4 isr_s4_s secondar y interrupt status 4 (shadow copy) page 63 0x00d8 isr_s5_s secondar y interrupt status 5 (shadow copy) page 63 table 6-2. general dma and rx-related registers (continued) offset name description page bit name description 31:7 res reserved 6 swi software interrupt; this bit is one-sh ot/auto-cleared, so it always reads as 0 5r x dr x d i s a b l e 4:3 res reserved 2 rxe receive (rx) enable 1:0 res reserved bit name description 31:2 rxdp rx descri ptor pointer 1:0 res reserved do not copy free datasheet http://www.datasheet-pdf.com/
atheros communications, inc. AR9223 single-chip 2x2 mimo mac/bb/radio for 802.11n wlans ? 47 company confidential october 2009 ? 47 6.2.1.3 configuration and status (cfg) offset: 0x0014 access: read/write cold reset: 0x0 warm reset: (same as cold reset) bit name reset description 31:19 res 0x0 reserved 18:17 full_threshold 0x0 pci core mast er request queue full threshold 0 use default value of 4 3:1 use indicated value 16:13 res 0x0 reserved 12 cfg_halt_ack 0x0 dma halt status 0 dma has not yet halted 1 dma has halted 11 cfg_halt_req 0x0 dma halt in preparation for reset request 0 dma logic operates normally 1 request dma logic to stop so software can reset the mac bit [12] of this register indi cates when the halt has taken effect; the dma halt is not recoverable; once software sets bit [11] to request a dma halt, software must wait for bit [12] to be set and reset the mac. 10 cfg_clkgate_dis 0x0 clock gating disable 0 allow clock gating in all dma blocks to operate normally 1 disable clock gating in all dma blocks (for debug use) 9 eeprom_busy 0x1 reserved; hardwired to 0 used as eeprom busy, which indicates whether the pci core is using off-chip serial ee prom. resets to 0x1, but will clear when pci core has completed loading the eeprom contents after the negation of pci_rst_l 8 phy_ok 0x0 phy ok; hardwired to 1 7:6 res 0x0 reserved 5 reg_cfg_adhoc 0x0 ap/ ad hoc indication 0ap mode mac is operating either as an access point (ap) or as a station (sta) in a bss 1ad hoc mode mac is operating as a sta in an independent basic service set (ibss) 4 mode_mmr 0x0 byteswap register access (mmr) data words 3 mode_rcv_data 0x0 byteswap rx data buffer words 2 mode_rcv_desc 0x0 byteswap rx descriptor words 1 mode_xmit_data 0x0 byteswap tx data buffer words 0 mode_xmit_desc 0x0 byteswap tx descriptor words do not copy free datasheet http://www.datasheet-pdf.com/
48 ? AR9223 single-chip 2x2 mimo mac/bb/radio for 802.11n wlans atheros communications, inc. 48 ? october 2009 company confidential 6.2.1.4 maximum interrupt rate threshold (mirt) offset: 0x0020 access: read/write cold reset: 0x0 warm reset: (same as cold reset) 6.2.1.5 interrupt global enable (ier) offset: 0x0024 access: read/write cold reset: 0x0 warm reset: (same as cold reset) 6.2.1.6 tx interrupt mitiga tion thresholds (timt) offset: 0x0028 access: read/write cold reset: 0x0 warm reset: (same as cold reset) bit name description 31:16 res reserved 15:0 intr_rate_thresh maximum interrupt rate threshold this register is described in s up to a maximum of 65.535 ms. if this register is 0x0, the interrupt mitigation mechanism is disabled. the maximum interrupt rate timer is started when either the txintm or rximtm status bits are set. txmintr or rxmintr are asserted at this time. no future txintm or rxintm events can cause the txmintr or txmintr to be asserted until this timer has expired. if b oth the txintm and rxintm status bits are set while the time r is expired then the txmintr and rxmintr will round robin between the two. bit name description 31:1 res reserved 0 reg_ier enable hardware signalling of interrupts bit name description 31:16 tx_first_pkt_thresh tx first packet threshold this register is in s up to a maximum of 65.535 ms. if this register is 0x0, the interrupt mitigation mechanism is disabled. the tx first packet timer starts counting after any tx completion . if the timer is still counting when the next tx completion occurs, it resets and starts over. the first tx packet timer expires when either the last tx packet threshold equals the last tx packet timer count or the first tx pa cket threshold equa ls the first tx packet timer count. 15:0 tx_last_pkt_thresh tx last packet threshold this register is in s up to a maximum of 65.535 ms. if this register is 0x0, the interrupt mitigation mechanism is disabled. the tx last packet timer starts counting after any tx completion . if the timer is still counting when the next tx completion occurs, it resets and starts over. the last tx packet timer expires when either the last tx packet threshold equals the last tx packet timer count or the first tx pa cket threshold equa ls the first tx packet timer count. do not copy free datasheet http://www.datasheet-pdf.com/
atheros communications, inc. AR9223 single-chip 2x2 mimo mac/bb/radio for 802.11n wlans ? 49 company confidential october 2009 ? 49 6.2.1.7 rx interrupt mitiga tion thresholds (rimt) offset: 0x002c access: read/write cold reset: (see field descriptions) warm reset: (same as cold reset) 6.2.1.8 tx configuration (txcfg) offset: 0x0030 access: read/write cold reset: (see field descriptions) warm reset: (same as cold reset) bit name description 31:16 rx_first_pkt_thresh recei ve first packet threshold this register is in s up to a maximum of 65.535 ms. if this register is 0x0, the interrupt mitigation mechanism is disabled. th e receive first packet timer starts counting after any receiv e completion. if the timer is still counting when the next receive completi on occurs, it resets and starts over. the first receive packet timer expires when either the last receive packet threshold equals the last receive pack et timer count or the first receive packet threshold equals the fi rst receive packet timer count. 15:0 rx_last_pkt_thresh receive last packet threshold this register is in s up to a maximum of 65.535 ms. if this register is 0x0, the interrupt mitigation mechanism is disabled. the receive last packet timer starts counting after any receiv e completion. if the timer is still counting when the next receive completi on occurs, it resets and starts over. the last receive packet timer expires when either the last receive packet threshold equals the last receive pack et timer count or the first receive packet threshold equals the fi rst receive packet timer count. bit name reset description 31:18 res 0x0 reserved 17 dis_retry _underrun 0x1 disable retry of underrun packets 0 underrun packets will retry indefinitely 1 underrun packets will quit after first underrun attempt and write status indicating underrun 16:15 res 0x0 reserved 14:10 res 0x0 reserved 9:4 txcfg_triglvl 0x1 frame trigger level specifies the minimum number of bytes, in units of 64 bytes, that must be dmaed into the pcu txfifo before the pcu initiates sending the frame on the air. resets to 0x1 (meaning 64b or a full frame, whichever occurs first). 3 res 0x0 reserved 2:0 txcfg_dma_size 0x5 maximum dma request size for master reads 04 b 18 b 216 b 332 b 464 b 5128 b 6256 b 7 reserved do not copy free datasheet http://www.datasheet-pdf.com/
50 ? AR9223 single-chip 2x2 mimo mac/bb/radio for 802.11n wlans atheros communications, inc. 50 ? october 2009 company confidential 6.2.1.9 rx configuration (rxcfg) offset: 0x0034 access: read/write cold reset: (see field descriptions) warm reset: (same as cold reset) 6.2.1.10 mib control (mibc) offset: 0x0040 access: read/write cold reset: (see field descriptions) warm reset: (same as cold reset) 6.2.1.11 timeout prescale (tops) offset: 0x0044 access: read/write cold reset: 0x0000 warm reset: (same as cold reset) bit name reset description 31:5 res 0x0 reserved 4:3 zero_len _dma_en 0x0 zero-length frame dma enable 0 disable dma of zero-length frames. in this mode, dma logic suppresses all zero-length frames. reception of ze ro-length frames is invisible to the host (they do not appear in host memory or consume a rx descriptor). 1reserved 2 enable dma of all zero-length frames. in this mode, all zero-length frames (chirps, double-chirps, and non-chirps ) dma into host memory just like normal (non-zero-length) frames. 3reserved 2:0 dma_size 0x4 maximum dma size for master writes (see the encodings for the register ?tx configuration (txcfg)? on page 49 ) bit name reset description 31:4 res 0x0 reserved 3 mibc_mibs 0x0 mib counter strobe. this one- shot bit always reads as zero. for writes: 0no effect 1 causes every mib counter to increment by one 2 mibc_aclr 0x1 clear all counters 1 mibc_frz 0x1 freeze all counters 0 mibc_wrn_comp 0x0 warning test indicator. read only bit name description 31:16 res reserved 15:0 tops timeout prescale count do not copy free datasheet http://www.datasheet-pdf.com/
atheros communications, inc. AR9223 single-chip 2x2 mimo mac/bb/radio for 802.11n wlans ? 51 company confidential october 2009 ? 51 6.2.1.12 rx no frame (rxnf) offset: 0x0048 access: read/write cold reset: 0x000 warm reset: (same as cold reset) 6.2.1.13 tx no frame (txnf) offset: 0x004c access: read/write cold reset: 0x000 warm reset: (same as cold reset) 6.2.1.14 rx frame gap timeout (rfgto) offset: 0x0050 access: read/write cold reset: 0x000 warm reset: (same as cold reset) 6.2.1.15 rx frame count limit (rfcnt) offset: 0x0054 access: read/write cold reset: (see field descriptions) warm reset: (same as cold reset) note: set to 0x1f (decimal 31) to disable bit name description 31:10 res reserved 9:0 rxnpto timeout count limit bit name description 31:20 res reserved 19:10 txnpmask qcu mask; specifies the set of qcus for which frame completions cause a reset of the txnofr timeout. 9:0 txnpto timeout count limit bit name description 31:10 res reserved 9:0 rpgto timeout count limit bit name reset description 31:5 res 0x0 reserved 4:0 rpcnt 0x1f frame count limit do not copy free datasheet http://www.datasheet-pdf.com/
52 ? AR9223 single-chip 2x2 mimo mac/bb/radio for 802.11n wlans atheros communications, inc. 52 ? october 2009 company confidential 6.2.1.16 global tx timeout (gtt) offset: 0x0064 access: read/write cold reset: 0x0 warm reset: (same as cold reset) 6.2.1.17 global tx timeout mode (gttm) offset: 0x0064 access: read/write cold reset: 0x0 warm reset: (same as cold reset) 6.2.1.18 carrier sense timeout (cst) offset: 0x006c access: read/write cold reset: 0x0 warm reset: (same as cold reset) bit name description 31:16 gtt_limit timeout limit (in tu: 1024 s) on reset, this value is set to 25 tu. 15:0 gtt_cnt timeout counter (in tu: 1024 s) the current value of the timeout counter that is reset on every transmit. if no tx frame is queued up and ready to transmit, the time out counter stays at 0 or else the counter increments every 1024 s. if the timeout counter is equal to or greater than the timeout limit, the global tr ansmit timeout interrupt is set in the isr. this mechanism can be used to detect whether a tx frame is ready and is unable to be transmitted. bit name description 31:5 res reserved 4 gtt_qcu_fr_disable disabl e qcu_fr_active for gtt if this bit is set, then gtt logic uses the pci_tx_qcu _status signal for gtt. if this bit is clear, then qcu_fr_active is used instead. 3 cst_usec_strobe cst s strobe if this bit is set, then the cst timer will not use the tu based strobe but rather use the s strobe to increment the timeout counter. 2 reset_on_chan_idle reset count on chan idle low. reset count every time channel idle is low. 1 ignore_chan_idle ignore channel idle if this bit is set then the gtt timer does not increment if the channel idle indicates the air is busy or nav is still counting down. 0 usec_strobe s strobe if this bit is set then the gtt time r will not use the tu based strobe but rather use a s strobe to increment the timeout counter. bit name description 31:16 cst_limit timeout limit (in tu: 1024 s). on reset, this value is set to 16 tu. 15:0 cst_cnt timeout counter (in tu: 1024 s) the current value of the timeout counter that is reset on every transmit. if no tx frame is queued up and read y to transmit, the timeout counter stays at 0 or else the counter increments every 1024 s. if the timeout counter is equal to or greater than the timeout limit then carrier sense timeout (cst) interrup t is set in the isr. this counter starts counting if any queues are ready to transmit. it continues counting when rx_clear is low, which is useful to determine whether the transmit is stuck because rx_clear is low for a long time. do not copy free datasheet http://www.datasheet-pdf.com/
atheros communications, inc. AR9223 single-chip 2x2 mimo mac/bb/radio for 802.11n wlans ? 53 company confidential october 2009 ? 53 6.2.1.19 primary interrupt status (isr_p) offset: 0x0080 access: read/wri te-one-to-clear cold reset: 0x0 warm reset: (same as cold reset) note: the bits that are logical ors of bits in the secondary isrs are generated by logically oring the secondary isr bits after the secondary isr bits have been masked with the appropriate bits from the corresponding secondary interrupt mask register. a write of one to a bit that is a logical or of bits in a secondary isr clears the secondary isr bits from which the primary isr bit is generated. e.g.: a write of a one to the txok bit (bit [6]) in isr_p clears all 10 txok bits in isr_s0 (bits [9:0] of ?secondary interrupt status 0 (isr_s0)? ). only the bits in this register (isr_p) and the primary interrupt mask register ( ?primary interrupt mask (imr_p)? ) control whether the mac?s inta# output is asserted. the bits in the several secondary interrupt status/mask registers control what bits are set in the primary interrupt status register; however, the imr_s* registers do not determine whether inta# is asserted. that is, inta# is asserted only when the logical and of isr_p and imr_p is non-zero. the secondary interrupt mask/status registers affect which bits are set in isr_p, but do not directly affect whether inta# is asserted. bit name description 31 rxintm rx completion interrupt after mitigation; either the first rx packet or last rx packet interrupt mitigation count has reached its threshold (see the register ?rx interrupt mitigation thresholds (rimt)? on page 49 ) 30 txintm tx completion interrupt after mitigation; either the first tx packet or last tx packet interrupt mitigation count has reached its threshold (see the register ?tx interrupt mitigation thresholds (timt)? on page 48 ) 29 hcfto hcf poll timeout 28 gentmr logical or of all generic timer bits in the secondary isr 5 which include the generic_timer_trigger[7:0], generic_timer_thresh[7:0], generic_timer_overflow 27 qtrig logical or of all qtrig bits in second ary isr 4; indicates that at least one qcu's frame scheduling trigger event has occurred 26 qcbrurn logical or of all qcbrurn bits in secondary isr 3; indicates that at least one qcu's frame scheduling trigger event occurr ed when no frames were present on the queue 25 qcbrovf logical or of all qc brovf bits in secondary isr 3; indicates that at least one qcu?s cbr expired counter has reached the value of the qcu?s cbr_ovf_thresh parameter 24 rxmintr rxmintr maximum receive interrupt rate; same as rxintm with the added requirement that maximum interrupt rate count has reached its threshold; this interrupt alternates with txmintr. 23 bcnmisc miscellaneous be acon-related interrupts this bit is the logical or of the cst, gtt, tim, cabend, dtimsync, bcnto, cabto, tsfoor, dtim, and tbtt_ti me bits in secondary isr 2. 22 hcfpoll received directed hcf poll 21 res reserved 20 bnr beacon not ready indicates that the qcu marked as being used for beacons received a dma beacon alert when the queue contained no frames. do not copy free datasheet http://www.datasheet-pdf.com/
54 ? AR9223 single-chip 2x2 mimo mac/bb/radio for 802.11n wlans atheros communications, inc. 54 ? october 2009 company confidential 19 txmintr txmintr maximum tx interrupt rate 18 bmiss the pcu indicates that is has not received a beacon during the previous n ( n is programmable) beacon periods 17 brssi the pcu indicates that the rssi of a beacon it has received has fallen below a programmable threshold 16 swba the pcu has signalled a software beacon alert 15 rxkcm key cache miss; a frame was received with a set key cache miss rx status bit 14 rxphy the phy signalled an error on a received frame 13 swi software interrupt signalled; see the register ?command (cr)? on page 46 12 mib one of the mib regs has reached its threshold 11 txurn logical or of all txurn bits in second ary isr 2. indicates that the pcu reported a txfifo underrun for at least one qcu?s frame 10 txeol logical or of all txeol bits in secondar y isr 1; indicates that at least one tx desc fetch state machine has no more tx descs available 9 txnofr have not transmitted a frame in txno fr timeout clocks. each qcu has only one txnofr bit; see the register ?tx no frame (txnf)? on page 51 8 txerr logical or of all txerr bits in second ary isr 1; indicates that at least one frame was completed with an error, regardless of whether the interreq bit was set 7 txdesc logical or of all txdesc bits in seco ndary isr 0; indicates th at at least one frame was sent and last desc had the interreq bit set 6 txok logical or of all txok bits in secondary isr 0; indicates that at least one frame was completed with no errors and at the requested rate, regardless of whether the interreq bit was set. 5 rxorn rxfifo overrrun 4 rxeol rx desc fetch logic has no more rx descs available 3 rxnofr no frame was received for rxnofr timeout clocks 2 rxerr the frame was received with errors 1 rxdesc the frame was received and the desc in terreq field was such that an interrupt was generated 0 rxok the frame was received with no errors bit name description do not copy free datasheet http://www.datasheet-pdf.com/
atheros communications, inc. AR9223 single-chip 2x2 mimo mac/bb/radio for 802.11n wlans ? 55 company confidential october 2009 ? 55 6.2.1.20 secondary interrupt status 0 (isr_s0) offset: 0x0084 access: read/wri te-one-to-clear cold reset: 0x0 warm reset: (same as cold reset) 6.2.1.21 secondary interrupt status 1 (isr_s1) offset: 0x0088 access: read/wri te-one-to-clear cold reset: 0x0 warm reset: (same as cold reset) bit description 31:26 reserved 25 txdesc for qcu 9 ... ... 17 txdesc for qcu 1 16 txdesc for qcu 0 15:10 reserved 9 txok for qcu 9 ... ... 1 txok for qcu 1 0 txok for qcu 0 bit description 31:26 reserved 25 txeol for qcu 9 ... ... 17 txeol for qcu 1 16 txeol for qcu 0 15:10 reserved 9 txerr for qcu 9 ... ... 1 txerr for qcu 1 0 txerr for qcu 0 do not copy free datasheet http://www.datasheet-pdf.com/
56 ? AR9223 single-chip 2x2 mimo mac/bb/radio for 802.11n wlans atheros communications, inc. 56 ? october 2009 company confidential 6.2.1.22 secondary interrupt status 2 (isr_s2) offset: 0x008c access: read/wri te-one-to-clear cold reset: 0x0 warm reset: (same as cold reset) 6.2.1.23 secondary interrupt status 3 (isr_s3) offset: 0x0090 access: read/wri te-one-to-clear cold reset: 0x0 warm reset: (same as cold reset) bit name description 31 tbtt_time tbtt-referenced time r interrupt; indicates the pcu?s tbtt-referenced timer has elapsed. 30 tsfoor tsf out of range; indicates that the corr ected tsf received from a beacon differs from the pcu's internal tsf by more than a (programmable) threshold 29 dtim a beacon was received with the dtim bit set and a dtim count value of zero. beacons with a set dtim bit but a non-zero dtim count do not generate it. 28 cabto cab timeout; a beacon was received that indicated that the sta should expect to receive cab traffic. however, the pcu's cab timeout expired either because the station received no cab traffic, or because the sta received some cab traffic but never received a cab frame with the more data bit clear in the frame control field (which would indicate the final cab frame). 27 bcnto beacon timeout; a tbtt oc curred and the sta began waiting to receive a beacon, but no beacon was received before the pcu?s beacon timeout expired 26 dtimsync dtim synchronization lost; a beacon was received that was expected to be a dtim but was not, or a beacon was received that was not expected to be a dtim but was 25 cabend end of cab traffic; a cab frame was received with the more data bit clear in the frame control field 24 tim a beacon was received with the lo cal station's bit set in the tim element 23 gtt global tx timeout; indicates the gtt count than the gtt limit 22 cst carrier sense timeout; indicates the cst count than the cst limit 21:10 reserved 9txurn for qcu 9 ... ... 1txurn for qcu 1 0txurn for qcu 0 bit description 31:26 reserved 25 qcbrurn for qcu 9 ... ... 17 qcbrurn for qcu 1 16 qcbrurn for qcu 0 15:10 reserved 9qcbrovf for qcu 9 1qcbrovf for qcu 1 ... ... 0qcbrovf for qcu 0 do not copy free datasheet http://www.datasheet-pdf.com/
atheros communications, inc. AR9223 single-chip 2x2 mimo mac/bb/radio for 802.11n wlans ? 57 company confidential october 2009 ? 57 6.2.1.24 secondary interrupt status 4 (isr_s4) offset: 0x0094 access: read/wri te-one-to-clear cold reset: 0x0 warm reset: (same as cold reset) 6.2.1.25 secondary interrupt status 5 (isr_s5) offset: 0x0094 access: read/wri te-one-to-clear cold reset: 0x0 warm reset: (same as cold reset) note: the trigger indicates that the tsf matched or exceeded the timer. the threshold is set when the tsf exceeds the timer by the generic_timer_thresh value. the generic_timer overflow occurs when the tsf exceeds the timer by such a large amount that tsf timer + period, indicating incorrect software programming. the generic_timer 0 threshold was removed because timer 0 is special and does not generate threshold event. bit description 31:10 reserved 9qtrig for qcu 9 ... ... 1qtrig for qcu 1 0qtrig for qcu 0 bit description 31 generic_timer 15 threshold ... ... 17 generic_timer 1 threshold 16 generic_timer overflow 15 generic_timer 15 trigger ... ... 1 generic_timer 1 trigger 0 generic_timer 0 trigger do not copy free datasheet http://www.datasheet-pdf.com/
58 ? AR9223 single-chip 2x2 mimo mac/bb/radio for 802.11n wlans atheros communications, inc. 58 ? october 2009 company confidential 6.2.1.26 primary interrupt mask (imr_p) offset: 0x00a0 access: read/write cold reset: 0x0 warm reset: (same as cold reset) note: only the bits in this register control whether the mac's inta# output are asserted. the bits in the secondary interrupt mask registers control what bits are set in the ?primary interrupt mask (imr_p)? register; however, the imr_s* registers do not determine whether inta# is asserted. bit description 31 rxintm interrupt enable 30 txintm interrupt enable 29 hcfto interrupt enable 28 gentmr interrupt enable 27 qtrig interrupt enable 26 qcbrurn interrupt enable 25 qcbrovf interrupt enable 24 rxmintr interrupt enable 23 bcnmisc interrupt enable 22 hcfpoll interrupt enable 21 reserved 20 bnr interrupt enable 19 txmintr interrupt enable 18 bmiss interrupt enable 17 brssi interrupt enable 16 swba interrupt enable 15 rxkcm interrupt enable 14 rxphy interrupt enable 13 swi interrupt enable 12 mib interrupt enable 11 txurn interrupt enable 10 txeol interrupt enable 9 txnofr interrupt enable 8 txerr interrupt enable 7 txdesc interrupt enable 6 txok interrupt enable 5 rxorn interrupt enable 4 rxeol interrupt enable 3 rxnofr interrupt enable 2 rxerr interrupt enable 1 rxdesc interrupt enable 0 rxok interrupt enable do not copy free datasheet http://www.datasheet-pdf.com/
atheros communications, inc. AR9223 single-chip 2x2 mimo mac/bb/radio for 802.11n wlans ? 59 company confidential october 2009 ? 59 6.2.1.27 secondary interrupt mask 0 (imr_s0) offset: 0x00a4 access: read/write cold reset: 0x0 warm reset: (same as cold reset) 6.2.1.28 secondary interrupt mask 1 (imr_s1) offset: 0x00a8 access: read/write cold reset: 0x0 warm reset: (same as cold reset) bit description 31:26 reserved 25 txdesc for qcu 9 interrupt enable ... ... 17 txdesc for qcu 1 interrupt enable 16 txdesc for qcu 0 interrupt enable 15:10 reserved 9 txok for qcu 9 interrupt enable ... ... 1 txok for qcu 1 interrupt enable 0 txok for qcu 0 interrupt enable bit description 31:26 reserved 25 txeol for qcu 9 interrupt enable ... ... 17 txeol for qcu 1 interrupt enable 16 txeol for qcu 0 interrupt enable 15:10 reserved 9 txerr for qcu 9 interrupt enable ... ... 1 txerr for qcu 1 interrupt enable 0 txerr for qcu 0 interrupt enable do not copy free datasheet http://www.datasheet-pdf.com/
60 ? AR9223 single-chip 2x2 mimo mac/bb/radio for 802.11n wlans atheros communications, inc. 60 ? october 2009 company confidential 6.2.1.29 secondary interrupt mask 2 (imr_s2) offset: 0x00ac access: read/write cold reset: 0x0 warm reset: (same as cold reset) 6.2.1.30 secondary interrupt mask 3 (imr_s3) offset: 0x00b0 access: read/write cold reset: 0x0 warm reset: (same as cold reset) bit name description 31 tbtt_time interrupt enable 30 tsfoor interrupt enable 29 dtim interrupt enable 28 cabto interrupt enable 27 bcnto interrupt enable 26 dtimsync interrupt enable 25 cabend interrupt enable 24 tim interrupt enable 23 gtt interrupt enable 22 cst interrupt enable 21:19 reserved 18 dperr interrupt enable 17 sserr interrupt enable 16 macbt interrupt enable 15:10 reserved 9 txurn for qcu 9 interrupt enable ... ... 1 txurn for qcu 1 interrupt enable 0 txurn for qcu 0 interrupt enable bit description 31:26 reserved 25 qcbrurn for qcu 9 interrupt enable ... ... 17 qcbrurn for qcu 1 interrupt enable 16 qcbrurn for qcu 0 interrupt enable 15:10 reserved 9 qcbrovf for qcu 9 interrupt enable ... ... 1 qcbrovf for qcu 1 interrupt enable 0 qcbrovf for qcu 0 interrupt enable do not copy free datasheet http://www.datasheet-pdf.com/
atheros communications, inc. AR9223 single-chip 2x2 mimo mac/bb/radio for 802.11n wlans ? 61 company confidential october 2009 ? 61 6.2.1.31 secondary interrupt mask 4 (imr_s4) offset: 0x00b4 access: read/write cold reset: 0x0 warm reset: (same as cold reset) 6.2.1.32 secondary interrupt mask 5 (imr_s5) offset: 0x0094 access: read/wri te-one-to-clear cold reset: 0x0 warm reset: (same as cold reset) note: the trigger indicates the tsf matched or exceeded the timer; threshold is set when the tsf exceeds the timer by the generic_timer_thresh value. the generic_timer overflow occurs when the tsf exceeds the timer by such a large amount that tsf timer + period, indicating incorrect software programming. the threshold generic_timer 0 was removed because timer 0 is special and does not generate a threshold event. bit description 31:10 reserved 9 qtrig for qcu 9 interrupt enable ... ... 1 qtrig for qcu 1 interrupt enable 0 qtrig for qcu 0 interrupt enable bit description 31 generic_timer_threshold 15 30 generic_timer_threshold 14 ... 18 generic_timer_threshold 2 17 generic_timer_threshold 1 16 generic_timer overflow enable 15 generic_timer 15 trigger enable ... ... 1 generic_timer 1 trigger enable 0 generic_timer 0 trigger enable do not copy free datasheet http://www.datasheet-pdf.com/
62 ? AR9223 single-chip 2x2 mimo mac/bb/radio for 802.11n wlans atheros communications, inc. 62 ? october 2009 company confidential 6.2.1.33 primary interrupt status read and clear (isr_p_rac) offset: 0x00c0 access: read-and-clear (no write access) cold reset: 0x0 warm reset: (same as cold reset) note: a read from this location atomically: copies all secondary isrs into the corresponding secondary isr shadow registers (isr_s0 is copied to isr_s0_s, etc.) clears all bits of the primary isr (isr_p) and all bits of all secondary isrs (isr_s0?isr_s4) returns the contents of the primary isr (isr_p) 6.2.1.34 secondary interrupt status 0 (isr_s0_s) offset: 0x00c4 access: read-only cold reset: 0x0 warm reset: (same as cold reset) 6.2.1.35 secondary interrupt status 1 (isr_s1_s) offset: 0x00c8 access: read-only cold reset: 0x0 warm reset: (same as cold reset) 6.2.1.36 secondary interrupt status 2 (isr_s2_s) offset: 0x00cc access: read-only cold reset: 0x0 warm reset: (same as cold reset) bit name description 31:0 isr_p same format as ?primary interrupt status (isr_p)? bit name description 31:0 isr_s0 same format as ?secondary interrupt status 0 (isr_s0)? bit name description 31:0 isr_s0 same format as ?secondary interrupt status 1 (isr_s1)? bit name description 31:0 isr_s0 same format as ?secondary interrupt status 2 (isr_s2)? do not copy free datasheet http://www.datasheet-pdf.com/
atheros communications, inc. AR9223 single-chip 2x2 mimo mac/bb/radio for 802.11n wlans ? 63 company confidential october 2009 ? 63 6.2.1.37 secondary interrupt status 3 (isr_s3_s) offset: 0x00d0 access: read-only cold reset: 0x0 warm reset: (same as cold reset) 6.2.1.38 secondary interrupt status 4 (isr_s4_s) offset: 0x00d4 access: read-only cold reset: 0x0 warm reset: (same as cold reset) 6.2.1.39 secondary interrupt status 5 (isr_s5_s) offset: 0x00d4 access: read-only cold reset: 0x0 warm reset: (same as cold reset) bit name description 31:0 isr_s0 same format as ?secondary interrupt status 3 (isr_s3)? bit name description 31:0 isr_s0 same format as ?secondary interrupt status 4 (isr_s4)? bit name description 31:0 isr_s0 same format as ?secondary interrupt status 5 (isr_s5)? do not copy free datasheet http://www.datasheet-pdf.com/
64 ? AR9223 single-chip 2x2 mimo mac/bb/radio for 802.11n wlans atheros communications, inc. 64 ? october 2009 company confidential 6.2.2 beacon handling table 6-3. ap in a bss: sending beacon and cab qcu description qcu 9 qcu 9 is used only for beacons qcu 9 feeds into dcu 9, and is the only qcu to feed into dcu 9 for qcu 9 for dcu 9 1. set fsp to dba-gated (see bits [3:0] of ?misc. qcu settings (q_misc)? ). 2. set the bit so the qcu sends beacons (q_misc bit [7]). 3. set the bit to disable cbrexpired counter increment if the local queue has no frames (q_misc bit [5]). 1. set the bit so dcu sends beacons (bit [16] of ?misc. dcu-specific settings (d_misc)? ). 2. set the bit to enable global lockout (set d_misc bits [18:17] to 0x2). 3. set both cw_min and cw_max to zero (see ?dcu-specific ifs settings (d_lcl_ifs)? ). qcu 8 qcu 8 is used only for cab (for a bss, cab is bcast and mcast frames) qcu 8 feeds into dcu 8, and is the only qcu to feed into dcu 8 for qcu 8 for dcu 8 1. set fsp to dba-gate 2. set the readytimeen bit and set the readytimeduration (rtd) to: rtd = beaconinterval ? ( sba ? dba ) beaconinterval is the interval between tbtts sba is the amount of ti me before tbtt that sba is generated dba is the amount of time before tbtt that dba is generated 3. set the bit to disable the cbrexpired counter increment if the beacon queue has no frames (bit [6] of ?misc. qcu settings (q_misc)? ). 4. set the bit to disable the cbrexpired counter increment if the local queue has no frames (q_misc bit [5]). 1. set the bit to enable global lockout. 2. software tasks at sba (all of these must occur before dba): build beacon and pass it to qcu 9. build cab and pass it to qcu 8. clear all tx filter bits for dcus 9 and 8. do not copy free datasheet http://www.datasheet-pdf.com/
atheros communications, inc. AR9223 single-chip 2x2 mimo mac/bb/radio for 802.11n wlans ? 65 company confidential october 2009 ? 65 table 6-4. sta in an ibss: send ing beacon and cab qcu description qcu 9 qcu 9 is used only for beacons qcu 9 feeds into dcu 9, and is the only qcu to feed into dcu 9 for qcu 9 for dcu 9 1. set fsp to dba-gated (q_misc bits [3:0]). 2. set the bit so the qcu sends beacons (q_misc bit [7]). 1. set dcu to send beacons (d_misc bit [16]). 2. set the bit to enable global lockout (set d_misc bits [18:17] to 0x2). 3. set both cw_min and cw_max to twice the usual cw_min value (refer to the 802.11 specifications). qcu 8 qcu 8 is used only for cab (for an ibss, cab is atims followed by data frames requiring preceding atim reception) qcu 8 feeds into dcu 8, and is the only qcu to feed into dcu 8 for qcu 8 for dcu 8 1. set fsp to dba-gate 2. set the readytimeen bit and set the readytimeduration (rtd) to: rtd = beaconinterval ? ( sba ? dba ) 3. set the bit to disable the cbrexpired counter increment if the beacon queue has no frames (bit [6] of ?misc. qcu settings (q_misc)? ). 4. set the bit to disable the cbrexpired counter increment if the beacon queue has no frames (q_misc bit [6]). 5. set the bit to disable the cbrexpired counter increment if the local queue has no frames (q_misc bit [5]). 6. set the bit to clear txe if readytime expires (q_misc bit [9]). 1. set the bit to enable global lockout. 2. software tasks at sba (all of these must occur before dba): build beacon and pass it to qcu 9. build cab and pass it to qcu 8. clear all tx filter bits for dcus 9 and 8. do not copy free datasheet http://www.datasheet-pdf.com/
66 ? AR9223 single-chip 2x2 mimo mac/bb/radio for 802.11n wlans atheros communications, inc. 66 ? october 2009 company confidential 6.2.3 qcu registers the qcu registers occu py the offset range 0x0800? 0x0a40 in the AR9223 address space. the AR9223 has ten qcus, numbered from 0 to 9. 6.2.3.1 tx queue descriptor (q_txdp) offset: 0x0800 + ( q < 2) access: read/write cold reset: (undefined) warm reset: (unaffected) 6.2.3.2 tx queue enable (q_txe) offset: 0x0840 access: read/write cold reset: 0x0 warm reset: (same as cold reset) note: writing a 1 in bit position n sets the txe bit for qcu n . writing a 0 in bit position n has no effect; in particular, it does not clear the txe bit for the qcu. table 6-5. qcu registers offset name description page 0x0800 + ( q << 2) [1] q_txdp transmit queue descriptor pointer page 66 0x0840 q_txe transmit queue enable page 66 0x0880 q_txd transmit queue disable page 67 0x08c0 + ( q << 2) [1] q_cbrcfg cbr configuration page 67 0x0900 + ( q << 2) [1] q_rdytimecfg readytime configuration page 67 0x0940 q_oneshotarm_sc oneshotarm set control page 68 0x0980 q_oneshotarm_cc oneshotarm clear control page 68 0x09c0 + ( q << 2) [1] q_misc miscellaneous qcu settings page 69 0x0a00 + ( q << 2) [1] q_sts miscellaneous qcu status page 71 0x0a40 q_rdytimeshdn readytimeshutdown status page 71 [1]the variable q in the register addresses refers to the qcu number. bit name description 31:2 txdp tx descriptor pointer 1:0 res reserved bit description 31:10 reserved 9enable qcu 9 ... ... 1enable qcu 1 0enable qcu 0 do not copy free datasheet http://www.datasheet-pdf.com/
atheros communications, inc. AR9223 single-chip 2x2 mimo mac/bb/radio for 802.11n wlans ? 67 company confidential october 2009 ? 67 6.2.3.3 tx queue disable (q_txd) offset: 0x0880 access: read/write cold reset: 0x0 warm reset: (same as cold reset) note: to stop transmission for qcu q: 1. write a 1 to qcu q's txd bit 2. poll the ?tx queue enable (q_txe)? register until qcu q? s txe bit is clear 3. poll qcu q? s ?misc. qcu status (q_sts)? register until its pending frame count (q_sts bits [1:0]) is zero 4. write a 0 to qcu q ?s txd bit at this point, qcu q has shut down and has no frames pending in its associated dcu. software must not write a 1 to a qcu?s txe bit when that qcu's txd bit is set; an undefined operation will result. soft ware must ensure that it sets a qcu?s txe bit only when the qcu?s txd bit is clear. it is fine to write a 0 to txe when txd is set, but this has no effect on the qcu. 6.2.3.4 cbr configuration (q_cbrcfg) offset: 0x08c0 + ( q < 2) access: read/write cold reset: 0x0 warm reset: (same as cold reset) 6.2.3.5 readytime configuration (q_rdytimecfg) offset: 0x0900 + ( q < 2) access: read/write cold reset: 0x0 warm reset: (same as cold reset) bit description 31:10 reserved 9enable qcu 9 ... ... 1enable qcu 1 0enable qcu 0 bit name description 31:24 cbr_ovf_thresh cbr overflow threshold 23:0 cbr_intv cbr interval in s bit name description 31:25 res reserved 24 rdytime_en readytime enable 0 disable readytime use 1 enable readytime use 23:0 rdytime_dur readytime duration in s do not copy free datasheet http://www.datasheet-pdf.com/
68 ? AR9223 single-chip 2x2 mimo mac/bb/radio for 802.11n wlans atheros communications, inc. 68 ? october 2009 company confidential 6.2.3.6 oneshotarm set control (q_oneshotarm_sc) offset: 0x0940 access: read/write cold reset: 0x0 warm reset: (same as cold reset) note: a read to this register returns the current state of all oneshotarm bits (qcu q ?s oneshotarm bit is returned in bit position q). 6.2.3.7 oneshotarm clear control (q_oneshotarm_cc) offset: 0x0980 access: read/write cold reset: 0x0 warm reset: (same as cold reset) note: a read to this register returns the current state of all oneshotarm bits (qcu q ?s oneshotarm bit is returned in bit position q). bit description 31:10 reserved 90no effect 1 set oneshot arm bit for qcu 9 ... ... 10no effect 1 set oneshot arm bit for qcu 1 00no effect 1 set oneshot arm bit for qcu 0 bit description 31:10 reserved 90no effect 1 clear oneshot arm bit for qcu 9 ... ... 10no effect 1 clear oneshot arm bit for qcu 1 00no effect 1 clear oneshot arm bit for qcu 0 do not copy free datasheet http://www.datasheet-pdf.com/
atheros communications, inc. AR9223 single-chip 2x2 mimo mac/bb/radio for 802.11n wlans ? 69 company confidential october 2009 ? 69 6.2.3.8 misc. qcu settings (q_misc) offset: 0x09c0 + ( q < 2) access: read/write cold reset: (see field descriptions) warm reset: (same as cold reset) bit name reset description 31:12 res 0x0 reserved 11 qcu_fr _abort _req_en 0x1 dcu frame early termination request control 0 never request early frame termination. once a frame enters the dcu, it will remain active until its normal retry count has been reached or the frame succeeds. 1 allow this qcu to request early frame termination. when requested, the dcu attempts to complete processing the frame more quickly than it normally would. 10 cbr_exp_cnt _clr_en 0x0 cbr expired counter force-clear contro l. write-only (always reads as zero). write of: 0no effect 1 resets the cbr expired counter to zero 9 txe_clr_on_ cbr_end 0x0 readytime expiration and veol hand ling policy 0 on expiration of readytime or on veol, the txe bit is not cleared. only reaching the physical end-of-queue (that is, a null linkptr) will clear txe 1 the txe bit is cleared on expira tion of readytime, on veol, and on reaching the physical end-of-queue 8 cbr_exp_inc_ limit 0x0 cbr expired counter limit enable 0 the maximum cbr expired counte r value is 255, but a cbrovf interrupt is generated when the counter reaches the value set in the cbr overflow threshold field of the ?cbr configuration (q_cbrcfg)? register. 1 the maximum cbr expired counter is limited to the value of the cbr overflow threshold field of the ?cbr configuration (q_cbrcfg)? register. note that in addition to limiting the maximum cbr expired counter to this value, a cbrovf interrupt is also generated when the cbr expired counter reaches the cbr overflow threshold. 7 qcu_is_bcn 0x0 beacon use indication. indicate s whether the qcu is being used for beacons 0 qcu is being used for non-beacon frames only 1 qcu is being used for beacon fram es (and possibly for non-beacon frames) 6 cbr_exp_inc_ dis_nobcnfr 0x0 disable the cbr expired counter increment if the frame scheduling trigger occurs and the qcu marked as being used for beacon transm ission (i.e., the qcu that has bit [7] set in its ?misc. qcu settings (q_misc)? register) contains no frames 0 increment the cbr expired co unter each time the frame scheduling trigger occurs, regardle ss of whether the beacon queue contains frames 1 increment the cbr expired coun ter only when both the frame scheduling trigger occurs and the beacon queue is valid (the beacon queue is valid whenever its txe is asserted) do not copy free datasheet http://www.datasheet-pdf.com/
70 ? AR9223 single-chip 2x2 mimo mac/bb/radio for 802.11n wlans atheros communications, inc. 70 ? october 2009 company confidential 5 cbr_exp_inc _dis_nofr 0x0 disable the cbr expired counter increment if the frame scheduling trigger occurs and the queue contains no frames 0 increment the cbr expired co unter each time the frame scheduling trigger occurs, rega rdless of whether the queue contains frames 1 increment the cbr expired coun ter only when both the frame scheduling trigger occurs and the queue is valid (the queue is valid whenever txe is asserted) 4 oneshot_en 0x0 oneshot enable 0 disable oneshot function 1 enable oneshot function note that oneshot must not be enab led when the qcu is set to an asap frame scheduling policy. 3:0 fsp 0x0 frame scheduling policy setting 0asap the qcu is enabled continuously. 1cbr the qcu is enabled under cont rol of the settings in the ?cbr configuration (q_cbrcfg)? register. 2dba-gated the qcu will be enabled at each occurrence of a dma beacon alert. 3tim-gated the qcu will be enabled whenever: in sta mode, the pcu indicates that a beacon frame has been received with the local sta?s bit set in the tim element in ibss mode, the pcu indicates that an atim frame has been received 4 beacon-sent-gated the qcu will be enabled when th e dcu that is marked as being used for beacon transmissi on (see bit [16] of the ?misc. dcu- specific settings (d_misc)? register) indicates that it has sent the beacon frame on the air 5 beacon-received-gated the qcu will be enabled when the pcu indicates that it has received a beacon. 6hcf poll gated the qcu will be enabled whenever the rx hcf poll event occurs; the signals come from the pcu when a directed hcf poll frame type is received with valid fcs. 15:7 reserved bit name reset description do not copy free datasheet http://www.datasheet-pdf.com/
atheros communications, inc. AR9223 single-chip 2x2 mimo mac/bb/radio for 802.11n wlans ? 71 company confidential october 2009 ? 71 6.2.3.9 misc. qcu status (q_sts) offset: 0x0a00 + ( q < 2) access: read-only cold reset: 0x0 warm reset: (same as cold reset) 6.2.3.10 readytimeshutdown status (q_rdytimeshdn) offset: 0x0a40 access: read/write cold reset: 0x0 warm reset: (same as cold reset) bit description 31:16 reserved 15:8 current value of the cbr expired counter 7:2 reserved 1:0 pending frame count indicates the number of frames this qcu pr esently has pending in its associated dcu. bit description 31:10 reserved 9 readytimeshutdown status for qcu 9 ... ... 1 readytimeshutdown status for qcu 1 0 readytimeshutdown status for qcu 0 on read, returns readytimeshutdown indication. write of: 0no effect 1 set oneshot arm bit for qcu 0 do not copy free datasheet http://www.datasheet-pdf.com/
72 ? AR9223 single-chip 2x2 mimo mac/bb/radio for 802.11n wlans atheros communications, inc. 72 ? october 2009 company confidential 6.2.4 dcu registers the dcu registers occu py the offset range 0x1000? 0x12f0 in the AR9223 address space. the AR9223 has ten dcus, numbered from 0 to 9. 6.2.4.1 qcu mask (d_qcumask) offset: 0x1000 + ( d < 2) access: read/write cold reset: 0x0 warm reset: (unaffected) note: to achieve lowest power consumption, software should set this register to 0x0 for all dcus that are not in use. the hardware detects that the qcu mask is set to zero and shuts down certain logic in response, helping to save power. table 6-6. qcu registers offset name description page 0x1000 + ( d << 2) [1] d_qcumask qcu mask page 72 0x1040 + ( d << 2) [1] d_lcl_ifs dcu-specific ifs settings page 73 0x1080 + ( d << 2) [1] d_retry_limit retry limits page 73 0x10c0 + ( d << 2) [1] d_chntime channeltime settings page 74 0x1100 + ( d << 2) [1] d_misc miscellaneous dc u-specific settings page 74 0x1030 d_gbl_ifs_sifs dcu-global ifs settings: sifs duration page 77 0x1070 d_gbl_ifs_slot dcu-global ifs settings: slot duration page 77 0x10b0 d_gbl_ifs_eif s dcu-global ifs settings: eifs duration page 77 0x10f0 d_gbl_ifs _misc dcu-global ifs settings: misc. parameters page 78 0x1270 d_txpse dcu transm it pause control/status page 79 0x12f0 d_txslotmask dcu transmission slot mask page 79 (varies) d_txblk dcu transmit filter bits page 80 [1]the variable d in the register addresses refers to the dcu number. bit name description 31:10 res reserved 9:0 qcu_mask qcu mask setting bit q means that qcu q is associated with (i.e., feeds into) this dcu. these register have reset values wh ich corresponding to a 1 to 1 mapping between qcus and dcus. a register offset of 0x1000 maps to 0x 1, 0x1004 maps to 0x2, 0x1008 maps to 0x4, etc. do not copy free datasheet http://www.datasheet-pdf.com/
atheros communications, inc. AR9223 single-chip 2x2 mimo mac/bb/radio for 802.11n wlans ? 73 company confidential october 2009 ? 73 6.2.4.2 dcu-specific ifs settings (d_lcl_ifs) offset: 0x1040 + ( d < 2) access: read/write cold reset: (see field descriptions) warm reset: (unaffected) 6.2.4.3 retry limits (d_retry_limit) offset: 0x1080 + ( d < 2) access: read/write cold reset: (see field descriptions) warm reset: (unaffected) bit name reset description when long aifs is 0: 31:28 res 0x0 reserved 27:20 data_aifs_d[7:0] 0x2 aifs va lue, in slots beyond sifs for example, a setting of 2 (the re set value) means aifs is equal to difs. note: although this field is 17 bits wide (including the 9 msbs accessed using the long aifs field), the maxi mum supported aifs value is 0x1fffc. setting the aifs value to 0x1fffd, 0x 1fffe, or 0x1ffff does not work correctly and causes the dcu to hang. 19:10 data_cw_max 0x3ff cw_max value; must be equal to a power of 2, minus 1 9:0 data_cw_min 0xf cw_min value; must be equal to a power of 2, minus 1 when long aifs is 1: 31:29 res 0x0 reserved 28 long_aifs [dcu_idx_d] 0x0 long aifs bit; used to read or writ e to the nine msbs of the aifs value 27:9 res 0x0 reserved 8:0 data_aifs_d[16:8] 0x2 upper nine bits of the aifs value (see bits [27:20] listed in this register) bit name reset description 31:20 res 0x20 reserved 19:14 sdfl 0x20 sta data failure limit specifies the number of times a fram e?s data exchange may fail before cw is reset to cw_min. note: a value of 0x0 is unsupported. 13:8 srfl 0x20 sta rts failure limit specifies the number of times a frame?s rts exchange may fail before the cw is reset to cw_min. note: a value of 0x0 is unsupported. 7:4 res 0x0 reserved 3:0 frfl 0x4 frame rts failure limit specifies the number of times a frame?s rts exchange may fail before the current transmission series is terminated. a frame?s rts exchange fails if rts is enabled for the fram e, but when the mac sends the rts on the air, no cts is received. note: a value of 0x0 is unsupported. do not copy free datasheet http://www.datasheet-pdf.com/
74 ? AR9223 single-chip 2x2 mimo mac/bb/radio for 802.11n wlans atheros communications, inc. 74 ? october 2009 company confidential 6.2.4.4 channeltime settings (d_chntime) offset: 0x10c0 + ( d < 2) access: read/write cold reset: 0x0 warm reset: (unaffected) 6.2.4.5 misc. dcu-specific settings (d_misc) offset: 0x1100 + ( d < 2) access: read/write cold reset: (see field descriptions) warm reset: (unaffected) bit name description 31:21 res reserved 20 channel_time _en channeltime enable 0 disable channeltime function 1 enable channeltime function 19:0 data_ct_mmr channeltime duration in s bit name reset description 31:24 res 0x0 reserved 23 retry_on _blown_ifs_en 0x0 blown ifs handling policy this setting controls how the dcu handles the case in which the dma of a frame takes so long that the ifs spacing is met before the frame trigger level is reached. 0 send the frame on the air an yway (i.e., ignore the ifs violation). this will cause the frame to be sent on the air at a time that is later than ca lled for in the 802.11 spec. 1 do not send the frame on the air. instead, act as if the frame had been sent on the air but failed and initiate the retry procedure. a retry will be char ged against the frame. if more retries are permitted, the frame will be retried. if the retry limit has been reached, the frame will fail. 22 virt_coll_cw _inc_en 0x0 virtual collision cw increment policy 0 virtual collisions do not increment (advance) the frame?s contention window (cw) 1 virtual collisions do increment the frame?s contention window (cw) 21 post_bkoff_skip 0x0 post-frame backoff disable 0 dcu performs a backoff after ea ch frame finishes, as required by the 802.11a spec 1 dcu skips the post-frame backoff (o r, equivalently, acts as if it always selects a post-frame backoff count of zero) do not copy free datasheet http://www.datasheet-pdf.com/
atheros communications, inc. AR9223 single-chip 2x2 mimo mac/bb/radio for 802.11n wlans ? 75 company confidential october 2009 ? 75 20 seqnum_freeze 0x0 sequence number increment disable 0 allow the dcu to use a normal sequence number progression (the dcu increments the sequ ence number for each new frame) 1 force the sequence number to be frozen at its current value 19 dcu_arb _lockout _ignore 0x0 dcu arbiter lockout ignore control 0 obey dcu arbiter lockouts from higher-priority dcus 1 ignore dcu arbiter lockouts from higher-priority dcus (i.e., allow the current dcu to arbitrat e for access to the pcu even if one or more higher-priority dcus is asserting a dcu arbiter lockout) 18:17 dcu_arb _lockout_if_en 0x0 dcu arbiter lockout control 0 no lockout. allows lower-priority dcus to arbitrate for access to the pcu concur rently with this dcu. 1 intra-frame lockout only. forces all lower-priority dcus to defer arbitrating for access to the pcu while the current dcu is either arbitrating for access to the pcu or performing an intra-frame backoff. 2 global lockout. forces all lower-priority dcus to defer arbitrating for access to the pcu whenever: at least one of the qcus that feed into the current dcu has a frame ready the current dcu is actively processing a frame (i.e., is not idle). this includes arbitrating for access to the pcu, performing an intra-frame or post-frame backoff, dma'ing frame data to the pcu, or waiting for the pcu to complete the frame. 3 reserved 16 dcu_is_brn 0x0 beacon use indication indicates whether the dcu is being used for beacons. 0 dcu is being used for non-beacon frames only 1 dcu is being used for beacon frames only 15:14 virt_coll _policy 0x0 virtual collision handling policy 0 default handling. a virtual collision is processed such as a collision on the air except that the retry count for the frame is not incremented (i.e., just perform the backoff). 1 ignore. virtual collisions are ignored (i.e., the dcu immediately rearbitrates for ac cess to the pcu without doing a backoff or incrementing the retry count). 3:2 reserved 13 res 0x0 reserved 12 mem_rd _data_pf 0x1 backoff persistence factor setting 0 new cw equals old cw 1 use binary-exponential cw progression 11:10 res 0x0 reserved bit name reset description do not copy free datasheet http://www.datasheet-pdf.com/
76 ? AR9223 single-chip 2x2 mimo mac/bb/radio for 802.11n wlans atheros communications, inc. 76 ? october 2009 company confidential 9 frag_burst _bkoff_en 0x0 fragment burst backoff policy this bit controls whether the dcu performs a backoff after each transmission of a fragment (i.e., a fr ame with the morefrag bit set in the frame control field). 0 the dcu handles fragment bursts normally 1 modified handling. the dcu performs a backoff after all fragments, even those tr ansmitted successfully. 8 frag_burst _wait_qcu_en 0x0 fragment burst frame st arvation handling policy this bit controls the dcu operation when the dcu is in the middle of a fragment burst and finds that the qc u sourcing the fragments does not have the next fragment available. 0 the dcu terminates the fragment burst. note that when this occurs, the remaining fragment s (when the qcu eventually has them available) will be sent as a separate fragment burst with a different sequence number. 1 the dcu waits for the qcu to have the next fragment available. while doing so, all other dcus will be unable to transmit frames. 7 ts_end_dis 0x0 end of transmission series cw reset policy this bit controls only whether the contention window is reset when transitioning from one tr ansmission series to the next within a single frame. the cw is reset per the 802. 11 spec when the entire frame attempt terminates (because the frame was sent successfully or because all transmission series failed). 0 reset the cw to cw_min at the end of each intraframe transmission series 1 do not reset the cw at the end of each intraframe transmission series 6 sfc_rst_at _ts_end_en 0x0 end of transmission series statio n rts/data failure count reset policy note that this bit controls only wh ether the two sta failure counts are reset when transitioning from one transmission series to the next within a single fr ame. the counts are reset per the 802.11 spec when the entire frame attempt terminates (e ither because the frame was sent successfully or because all transmission series failed). 0 do not reset the station rts failure count or the sta data failure count at the end of each transmission series 1 reset both the station rts failure count and the sta data failure count at the end of each transmission series 5:0 data _bkoff_thresh 0x2 backoff threshold setting determines the backoff count at whic h the dcu will initiate arbitration for access to the pcu and commit to sending the frame. bit name reset description do not copy free datasheet http://www.datasheet-pdf.com/
atheros communications, inc. AR9223 single-chip 2x2 mimo mac/bb/radio for 802.11n wlans ? 77 company confidential october 2009 ? 77 6.2.4.6 dcu-global ifs settings: sifs duration (d_gbl_ifs_sifs) offset: 0x1030 access: read/write cold reset: 640 (16 s at 40 mhz) warm reset: (unaffected) 6.2.4.7 dcu-global ifs settings: slot duration (d_gbl_ifs_slot) offset: 0x1070 access: read/write cold reset: 360 (9 s at 40 mhz) warm reset: (unaffected) 6.2.4.8 dcu-global ifs settings: eifs duration (d_gbl_ifs_eifs) offset: 0x10b0 access: read/write cold reset: 3480 (87 s at 40 mhz) warm reset: (unaffected) bit name description 31:16 res reserved 15:0 sifs_dur sifs duration in core clocks (40 mhz in non-turbo mode, 80 mhz in turbo mode) bit name description 31:16 res reserved 15:0 slot_dur slot duration in core clocks (40 mhz in non-turbo mode, 80 mhz in turbo mode) bit name description 31:16 res reserved 15:0 eifs_dur eifs duration in core clocks (40 mhz in non-turbo mode, 80 mhz in turbo mode) do not copy free datasheet http://www.datasheet-pdf.com/
78 ? AR9223 single-chip 2x2 mimo mac/bb/radio for 802.11n wlans atheros communications, inc. 78 ? october 2009 company confidential 6.2.4.9 dcu-global ifs settings: misc. parameters (d_gbl_ifs_misc) offset: 0x10f0 access: read/write cold reset: (see field descriptions) warm reset: (unaffected) bit name reset description 31:29 res 0x0 reserved 26:25 chan_slot _win_dur 0x0 slot transmissi on window length specifies the number of core clocks af ter a slot boundary during which the mac is permitted to send a frame. spec ified in units of 8 core clocks, with the value 0x0 being special. if set to a value of 0x0 (the reset value), the mac is permitted to send at any point in the slot. 28 ignore _backoff 0x0 ignore back off allows the dcu to ignore backoff as well as eifs; it should be set during fast channel change to guarantee low latency and flush the tx pipe. 27 chan_slot _always 0x0 force transmission al ways on slot boundaries when bits [26:25] of this register ar e non-zero, the mac transmits on slot boundaries as required by the 802.11 spec. when bits [26:25] are not 0x0 and this bit is non-zero, the mac al ways transmits on slot boundaries. 24 lfsr_slice _random_dis 0x0 random lfsr slice selection disable 0 allow the ifs logic to randomly ge nerate the lfsr slice select value (see bits [2:0] of this register). the random selection ensures independence of the lfsr output values both for nodes on different pci busses but on the same network as well as for multiple nodes connected to the same physical pci bus. 1 disable random lfsr slice sele ction and use the value of the lfsr slice select field (bits [2 :0] of this register) instead 23 aifs_rst _uncond 0x0 aifs counter reset po licy (debug use only) 0 reset the aifs counter only when pcu_rst_aifs is asserted and the counter already has reached aifs 1 reset the aifs counter unconditionally whenever pcu_rst_aifs is asserted 22 sifs_rst _uncond 0x0 sifs counter reset policy (debug use only) 0 reset the sifs counter only when pcu_rst_sifs is asserted and the counter already has reached sifs 1 reset the sifs counter unconditionally whenever pcu_rst_sifs is asserted 21:3 res 0x0 reserved 2:0 lfsr_slice_sel 0x0 lfsr slice select determines which slice of the internal lfsr will generate the random sequence used to determine backof f counts in the pcu?s dcus and scrambler seeds. this allows different stas to contain different lfsr slice values (e.g., by using bits from the mac addres s) to minimize random sequence correlations among stas in the same bss/ibss. note: this field affects the mac only when the random lfsr slice selection disable bit (bit [24] of this register) is set. when random lfsr slice selection is enabled (the default), this field is ignored. do not copy free datasheet http://www.datasheet-pdf.com/
atheros communications, inc. AR9223 single-chip 2x2 mimo mac/bb/radio for 802.11n wlans ? 79 company confidential october 2009 ? 79 6.2.4.10 dcu tx pause control/status (d_txpse) offset: 0x1270 access: read/write cold reset: (see field descriptions) warm reset: (unaffected) 6.2.4.11 dcu transmission slot mask (d_txslotmask) offset: 0x12f0 access: read/write cold reset: 0x0 warm reset: (unaffected) note: when bits [26:25] of the ?dcu-global ifs settings: misc. parameters (d_gbl_ifs_misc)? register are non-zero, d_txslotmask controls which slots dcus can start frame transmission on. the slot occurring coincident with sifs elapsing is slot 0. slot numbers increase thereafter, whether the channel was idle or busy during the slot. if bits [26:25] of d_gbl_ifs_misc are zero, this register has no effect. bit name reset description 31:17 res 0x0 reserved 16 tx_paused 0x1 tx pause status 0 tx pause request has not yet taken effect, so some dcus for which a transmission pause reques t has been issued using bits [9:0] of this register are still transmitting and have not paused. 1 all dcus for which a transmission pause request has been issued via bits [9:0] of this register, if any, have paused their transmissions. note that if no transmission pause request is pending (i.e., bits [9:0] of this re gister are all set to 0), then this tx pause status bit will be set to one. 15:10 res 0x0 reserved 9:0 dcu_reg_txpse 0x0 request that some subset of the dcus pause transmission. for bit d of this field (9 d 0): 0 allow dcu d to continue to transmit normally 1request that dcu d pause transmission as soon as it is able bit description 31:16 reserved 15 specifies whether transmission may start on slot numbers that are congruent to 15 (mod 16) 0 transmission may start on such slots 1 transmission may not start on such slots ... ... 1 specifies whether transmission may start on slot numbers that are congruent to 1 (mod 16) 0 transmission may start on such slots 1 transmission may not start on such slots 0 specifies whether transmission may start on slot numbers that are congruent to 0 (mod 16) 0 transmission may start on such slots 1 transmission may not start on such slots do not copy free datasheet http://www.datasheet-pdf.com/
80 ? AR9223 single-chip 2x2 mimo mac/bb/radio for 802.11n wlans atheros communications, inc. 80 ? october 2009 company confidential 6.2.4.12 dcu tx filter bits (d_txblk) offset: varies (see table 6-7 ) access: read/write cold reset: 0x0 warm reset: (unaffected) each dcu has 128 tx filter bits, for a total of 10 * 128=1280 tx filter bits for all ten dcus. for reads of the tx filter bits, the 1280 bits are accessed via reads within a range of 64 32-bit register locations. for writes of the tx filter bits, only three of the 64 register locations are used. one location allows specific bits of a specific dcu?s tx filter bits to be set or cleared. two other locations allow all 128 tx filter bits for any subset of the ten dcus to be set or cleared atomically. for both reads and writes, the pci offset issued by the host is mapped to one of the 64 register locations. the 6-bit internal address resulting from mapping is called mmr_addr, and its value controls what portion of the tx filter bits is affected by the host?s register read or write. in general, the pci offset that maps to the internal mmr_addr is given by the equation: pci offset = 0x1038 + ((mmr_addr & 0x1f) << 6) + ((mmr_addr & 0x20) >> 3) thus the proper pci offset can be determined from the desired mmr_addr (see table 6-7 ). table 6-7. mmr_addr and pci offset mmr_addr pci offset 00 x 1 0 3 8 10 x 1 0 7 8 2 0x10b8 3 0x10f8 4 0x1138 5 0x1178 6 0x11b8 7 0x11f8 80 x 1 2 3 8 90 x 1 2 7 8 10 0x12b8 11 0x12f8 12 0x1338 13 0x1378 14 0x13b8 15 0x13f8 16 0x1438 17 0x1478 18 0x14b8 19 0x14f8 20 0x1538 21 0x1578 22 0x15b8 23 0x15f8 24 0x1638 25 0x1678 26 0x16b8 27 0x16f8 28 0x1738 29 0x1778 30 0x17b8 31 0x17f8 ... ... 48 0x143c 49 0x147c table 6-7. mmr_addr and pci offset mmr_addr pci offset do not copy free datasheet http://www.datasheet-pdf.com/
atheros communications, inc. AR9223 single-chip 2x2 mimo mac/bb/radio for 802.11n wlans ? 81 company confidential october 2009 ? 81 writes only three register locations (mmr_addr values) are supported for writes. writes to other values yield undefined results and may corrupt tx filter bits. reads table 6-8. mmr_addr usage for tx filter bits (write data) mmr_addr description 49 sets all 128 filter bits for each dcu that has a 1 in bits [9:0] of the write data (e.g., a write of 0x5 to address 49 causes all 128 filter bi ts for dcus 0 and 2 to be set) 48 clears all 128 filter bits for each dcu that has a 1 in bits [9:0] of the write data (e.g., a write of 0x5 to address 48 causes all 128 filter bi ts for dcus 0 and 2 to be cleared) 0 allows individual bits of a particular dcu?s 128 tx filter bits to modify. the write data determines which bits are affected and what operation is perfor med. the write data is split into several fields: 31:28 reserved 27:24 command; determines what operation will be performed on the selected filter bits: 0 clear the selected bits 1 set the selected bits 15:2 reserved 23:20 dcu number; determines which dcu?s tx filter bits are affe cted by writes. setting this field to a value of d (9 d 0) causes dcu d ?s tx filter bits to be affected by the write. 19:16 slice number; selects a 16-bit bitslice from the selected dcu? s 128 affected tx filter bits: 0 filter bits [15:0] are affected 1 filter bits [31:16] are affected ... ... 7 filter bits [127:112] are affected 15:8 reserved 15:0 bitmask; controls which bits within the selected bitslice are affected. bit n (15 n 0) of the bitmask affects bit n of the selected bitslice (see examples): 0 bit n remains unchanged 1 bit n of the selected bitslice is modified per the command field (bits [ 27:24]) example write data example effect 0x130404 clears bits [50] and [58] of dcu 1?s tx filter bits 0x00978001 clears bits [127] and [112] of dcu 9?s tx filter bits table 6-9. mmr_addr usage for tx filter bits (read data) mmr_addr description 7:4 returns filter bits for dc u 1, bits [31:0] ? [127:96] 49:48 no effect 39:36 returns filter bits for dc u 9, bits [31:0] ? [127:96] ... ... 3 returns filter bits fo r dcu 0, bits [127:96] 2 returns filter bits for dcu 0, bits [95:64] 1 returns filter bits for dcu 0, bits [63:32] 0 returns filter bits for dcu 0, bits [31:0] do not copy free datasheet http://www.datasheet-pdf.com/
82 ? AR9223 single-chip 2x2 mimo mac/bb/radio for 802.11n wlans atheros communications, inc. 82 ? october 2009 company confidential 6.2.5 eeprom interface registers this eeprom registers access the external eeprom. upon power reset, a state machine inside the host interface reads the eeprom and writes registers within the AR9223. the eeprom map is shown in figure 6-1 : each eeprom location is 16 bits wide. as shown in figure 6-1 , the first location must contain the 16-bit word a55a, indicating that the eeprom is valid. if the first location is not this value, then the state machine assumes the eeprom contents have been corrupted and immediately stops running. the next eeprom location contains the mask word as described. location 2 contains an address pointer to the next valid data segment. each data segment consists of three locations: a 16-bit address location and two locations for the 32-bit write data as shown in figure 6-1 . the state machine reads each data segment and writes to the corresponding AR9223 register. the state machine stops when it comes to an address equal to ffff. 6.2.6 host interface registers figure 6-1. eeprom address map table 6-10. host interface registers offset name description page 0x4000 h_rc reset the mac ahb/apb interface page 83 0x4018 h_timeout host timeout page 83 0x401c h_eeprom_ctrl eeprom control page 83 0x4020 h_srev_id mac silicon revision id page 84 0x4028 h_intr_cause_clr i nterrupt cause clear page 84 0x4028 h_intr_sync_caus synchronous interrupt cause page 85 0x402c h_intr_sync_enab sync hronous interrupt enable page 85 0x4030 h_intr_asyn_mask asynchronous interrupt mask page 85 0x4034 h_intr_syn_mask synchronous interrupt mask page 85 0x4038 h_intr_asyn_caus asynchronous interrupt cause page 86 0x403c h_intr_asyn_enab asynch ronous interrupt enable page 86 0x4048 h_gpio_in_out gp io input and output page 86 0x404c h_gpio_oe_bits gpio output enable bits page 87 0x4050 h_gpio_irq_polar gpio interrupt polarity page 87 0x4054 h_gp_inpt_en_val gpio input enable and value page 87 0x405c h_gp_inpt_mux2 gpio input mux2 page 88 0x4060 h_gp_outpt_mux1 gpio output mux1 page 88 0x4064 h_gp_outpt_mux2 gpio output mux2 page 88 0x406c h_input_state input values page 89 0x4078 h_pci_clkrun pci clkrun page 89 0x407c h_eep_sts_data eeprom status and read data page 90 0x4084 h_rfsilent rfsilent-related registers page 90 0x4088 h_gpio_pdpu gpio pull-up/pull-down page 91 0x408c h_gpio_ds gpio drive strength page 91 do not copy free datasheet http://www.datasheet-pdf.com/
atheros communications, inc. AR9223 single-chip 2x2 mimo mac/bb/radio for 802.11n wlans ? 83 company confidential october 2009 ? 83 6.2.6.1 reset the mac ahb/apb interface (h_rc) offset: 0x4000 access: read/write reset value: 0000_0000 6.2.6.2 host timeout (h_timeout) offset: 0x4018 access: read/write reset value: 1000_1000 6.2.6.3 eeprom control (h_eeprom_ctrl) offset: 0x401c access: read/write reset value: 0000_00fc bit description 31:9 reserved 8 0 normal host master interface 1 hold pci master interface in reset 7:2 reserved 1 0 normal mac apb interface operation 1 hold mac apb interface in reset 0 0 normal mac ahb interface operation 1 hold mac ahb interface in reset bit description 31:16 ahb bus timeout counter for dma transfers 15:0 apb bus timeout counter for register access bit description 31:26 reserved 25:10 eeprom protect mask 9 eeprom is corrupt 8 eeprom not present 7:2 clkdiv value for the apb eeprom module apb_eeprom 1:0 reserved do not copy free datasheet http://www.datasheet-pdf.com/
84 ? AR9223 single-chip 2x2 mimo mac/bb/radio for 802.11n wlans atheros communications, inc. 84 ? october 2009 company confidential 6.2.6.4 mac silicon revision id (h_srev_id) offset: 0x4020 access: read-only reset value: 0008_50ff table 6-11 describes all of the signals capable of generating a system interrupt and lists their corresponding bits. the bits are the same for synchronous as well as asynchronous interrupts. 6.2.6.12 interrupt cause clear (h_intr_cause_clr) offset: 0x4028 access: write-only reset value: 0000_0000 bit description 31:18 2 version 17:12 5 type 11:8 2 revision 7:0 255 old revision table 6-11. system interrupt registers: bit descriptions bit name description 31:18 res reserved 17 mac_sleep_access software is trying to access a register within the mac while it is asleep 16 mac_asleep the mac has gone to sleep 15 mac_awake the mac has become awake 14 pm_access the ahb master is requesting that a dma transfer to the core while it is asleep 13 local_timeout a local bus timeout has occurred 12:4 res reserved 3 apb_timeout no response from one of the AR9223 modules within the programmed timeout period during a register access 2 eeprom_illegal_access software attempted to either access a protec ted area within the eeprom, or access the eeprom while it is busy or absent 1 mac_irq the mac has requested an interrupt 0 rtc_irq the rtc is in shutdown state bit description 31:0 writing a 1 to any bit in this regist er clears the corresponding bit in the ?synchronous interrupt cause (h_intr_sync_caus)? register. see table 6-11 for bit descriptions. do not copy free datasheet http://www.datasheet-pdf.com/
atheros communications, inc. AR9223 single-chip 2x2 mimo mac/bb/radio for 802.11n wlans ? 85 company confidential october 2009 ? 85 6.2.6.13 synchronous interrupt cause (h_intr_sync_caus) offset: 0x4028 access: read-only reset value: 0000_0000 6.2.6.14 synchronous interrupt enable (h_intr_sync_enab) offset: 0x402c access: read/write reset value: 0000_0000 6.2.6.15 asynchronous interrupt mask (h_intr_asyn_mask) offset: 0x4030 access: read/write reset value: 0000_0002 6.2.6.16 synchronous interrupt mask (h_intr_syn_mask) offset: 0x4034 access: read/write reset value: 0000_0000 bit description 31:0 setting any bit in this regist er indicates that the correspondin g interrupt has been triggered in synchronous mode; for any bit to be to set in this register, the corresponding bit in the ?synchronous interrupt enable (h_intr_sync_enab)? register must also be set. see table 6-11 for bit descriptions. bit description 31:0 setting any bit in this register allows the corres ponding interrupt signal to set its corresponding bit in the ?synchronous interrupt ca use (h_intr_sync_caus)? register. see table 6-11 for bit descriptions. bit description 31:0 setting any bit in this register allows the corr esponding interrupt signal to trigger a pci interrupt provided that the corresponding ?asynchronous interrupt cause (h_intr_asyn_caus)? register bit is set. note that for this register bit to be set, the corresponding ?asynchronous interrupt enable (h_intr_asyn_enab)? register bit must also be set by software. see table 6-11 for bit descriptions. bit description 31:0 setting any bit in this register allows the corr esponding interrupt signal to trigger a pci interrupt provided that the corresponding ?synchronous interrupt cause (h_intr_sync_caus)? register bit is set. note that for this register bit to be set, the corresponding ?synchronous interrupt enable (h_intr_sync_enab)? register bit must also be set by software. see table 6-11 for bit descriptions. do not copy free datasheet http://www.datasheet-pdf.com/
86 ? AR9223 single-chip 2x2 mimo mac/bb/radio for 802.11n wlans atheros communications, inc. 86 ? october 2009 company confidential 6.2.6.17 asynchronous interrupt cause (h_intr_asyn_caus) offset: 0x4038 access: read-only reset value: 0000_0000 6.2.6.18 asynchronous interrupt enable (h_intr_asyn_enab) offset: 0x403c access: read/write reset value: 0000_0002 6.2.6.19 gpio input and output (h_gpio_in_out) offset: 0x4048 access: see field description reset value: 000f_8c00 bit description 31:0 setting any bit in this regist er indicates that the correspondin g interrupt has been triggered in asynchronous mode. for any bit to be to set in this register, the co rresponding bit in the ?asynchronous interrupt enable (h_intr_asyn_enab)? register must also be set. see table 6-11 for bit descriptions. bit description 31:0 setting any bit in this regist er indicates that the correspondin g interrupt has been triggered in asynchronous mode. for any bit to be to set in this register, the co rresponding bit in the ?asynchronous interrupt enable (h_intr_asyn_enab)? register must also be set. see table 6-11 for bit descriptions. bit access description 31:20 r/w reserved 19:20 ro actual value of each gpio signal 9:0 r/w output value of each gpio used when the corresponding gpio enable bi ts and gpio output mux registers are set correctly do not copy free datasheet http://www.datasheet-pdf.com/
atheros communications, inc. AR9223 single-chip 2x2 mimo mac/bb/radio for 802.11n wlans ? 87 company confidential october 2009 ? 87 6.2.6.20 gpio output enable bits (h_gpio_oe_bits) offset: 0x404c access: read/write reset value: 0000_0000 note: each 2-bit field controls the drive mechanism for each gpio. the mapping for this 2-bit field is: 0 = never drive output 1 = drive if the output is low 2 = drive if the output is high 3 = always drive output 6.2.6.21 gpio interrupt polarity (h_gpio_irq_polar) offset: 0x4050 access: read/write reset value: 0000_0000 6.2.6.22 gpio input enable and value (h_gp_inpt_en_val) offset: 0x4054 access: read/write reset value: 0000_0000 bit description 31:20 reserved 19:18 configuration for gpio9 17:16 configuration for gpio8 15:14 configuration for gpio7 13:12 configuration for gpio6 11:10 configuration for gpio5 9:8 configuration for gpio4 7:6 configuration for gpio3 5:4 configuration for gpio2 3:2 configuration for gpio1 1:0 configuration for gpio0 bit description 31:10 reserved 9:0 gpio interrupt polarity 0 corresponding gpio can interrupt if it is high 1 corresponding gpio can interrupt system if it is low bit description 31:18 reserved 17 0 jtag enabled; gpio[4:0] is controlled by jtag controller 1 jtag disabled; software must set this bit before using gpio[4:0] 16 0 rtc reset controlled entirely by software 1 rtc reset controllable through a gpio pin and software 15:0 reserved do not copy free datasheet http://www.datasheet-pdf.com/
88 ? AR9223 single-chip 2x2 mimo mac/bb/radio for 802.11n wlans atheros communications, inc. 88 ? october 2009 company confidential 6.2.6.23 gpio input mux2 (h_gp_inpt_mux2) offset: 0x405c access: read/write reset value: 0000_e000 6.2.6.24 gpio output mux1 (h_gp_outpt_mux1) offset: 0x4060 access: read/write reset value: 0000_0000 note: see table 6-12 . 6.2.6.25 gpio output mux2 (h_gp_outpt_mux2) offset: 0x4064 access: read/write reset value: 000e_8000 note: see table 6-12 . bit description 31:12 reserved 11:8 gpio_input_mux[8] for rtc reset input 7:0 reserved bit description 31:26 reserved 29:25 gpio_output_mux[5] 24:20 gpio_output_mux[4] 19:15 gpio_output_mux[3] 14:10 gpio_output_mux[2] 9:5 gpio_output_mux[1] 4:0 gpio_output_mux[0] bit description 31:20 reserved 19:15 gpio_output_mux[9] 14:10 gpio_output_mux[8] 9:5 gpio_output_mux[7] 4:0 gpio_output_mux[6] do not copy free datasheet http://www.datasheet-pdf.com/
atheros communications, inc. AR9223 single-chip 2x2 mimo mac/bb/radio for 802.11n wlans ? 89 company confidential october 2009 ? 89 table 6-12 shows the output mux value for each gpio. 6.2.6.13 input values (h_input_state) offset: 0x406c access: read-only reset value: 0000_0013 6.2.6.14 pci clkrun (h_clkrun) offset: 0x4078 access: read/write reset value: 0000_0200 table 6-12. output mux values for each gpio bit description 31 set gpio output to the value set in the gpio output register 30:29 reserved 28 set gpio to rx_clear_extension 27:8 reserved 7 set gpio to pci_clkrun signal 6 set gpio to mac power led signal 5 set gpio to mac network signal 4 set gpio to rx-clear-external signal 3 set gpio to tx-frame signal 2:1 reserved 0 set gpio output to value se t in the gpio output register bit description 31:7 reserved 6 status of tx_frame from the mac 5 status of rx_clear_external from the mac 4 status of the power led from the mac 3 status of the network led from the mac 2 status of pci_clkr un from pci core 1 status of power_led from pci core 0 reserved bit description 31:1 clkrun delay parameter 0 0 allow the pci core to deassert clkrun and stop the clock 1 force the pci core to assert clkrun and keep the clock running do not copy free datasheet http://www.datasheet-pdf.com/
90 ? AR9223 single-chip 2x2 mimo mac/bb/radio for 802.11n wlans atheros communications, inc. 90 ? october 2009 company confidential 6.2.6.15 eeprom status and read data (h_eep_sts_data) offset: 0x407c access: read-only reset value: 0000_0000 6.2.6.16 rfsilent-related registers (h_rfsilent) offset: 0x4084 access: read/write reset value: 0000_0000 bit description 31:20 reserved 19 this bit indicates that software attempted to ac cess the eeprom even though it is not present 18 this bit indicates that the last software access to the eeprom occurred to a protected area within the eeprom and was therefore not forwarded to the eeprom 17 this bit indicates that the last software access to the eeprom occurred when it was busy and was therefore not forwarded to the eeprom 16 0 eeprom is idle 1 eeprom is busy 15:0 results of the last eeprom read transfer bit description 31:3 reserved 2rtc reset invert this bit is only relevant if rtc reset override (bit [16]) in the ?gpio input enable and value (h_gp_inpt_en_val)? register is set. if the rtc reset overr ide bit is cleared, then the rtc reset is entirely controlled by software (bi t [0] of the register at 0x7040). 0 a low in the corresponding gpio input holds the rtc in reset; a high allows the rtc reset to be controlled by software 1 a high in the corresponding gp io input holds the rtc in reset; a low allows the rtc reset to be controlled by software 1 rfsilent_force sign al to the baseband 0 rfsilent polarity 0 do not invert the rfsilent_bb_l signal to the baseband 1 invert the rfsilent_bb_l signal to the baseband do not copy free datasheet http://www.datasheet-pdf.com/
atheros communications, inc. AR9223 single-chip 2x2 mimo mac/bb/radio for 802.11n wlans ? 91 company confidential october 2009 ? 91 6.2.6.17 gpio pull-up/pull-down (h_gpio_pdpu) offset: 0x4088 access: read/write reset value: 0000_0001 note: each 2-bit field controls the drive mechanism for each gpio. the mapping for this 2-bit field is: 0 = no pull-up or pull-down 1 = pull-down 2 = pull-up 3 = reserved 6.2.6.18 gpio drive strength (h_gpio_ds) offset: 0x408c access: read/write reset value: 0000_0000 note: every 2-bit field corresponds to a particular value; the possibilities are: 0 = default drive strength = 6 ma 1 = drive strength = 12 ma 2 = drive strength = 18 ma 3 = drive strength = 24 ma bit description 31:20 reserved 19:18 configuration for gpio9 17:16 configuration for gpio8 15:14 configuration for gpio7 13:12 configuration for gpio6 11:10 configuration for gpio5 9:8 configuration for gpio4 7:6 configuration for gpio3 5:4 configuration for gpio2 3:2 configuration for gpio1 1:0 configuration for gpio0 bit description 31:20 reserved 19:18 configuration for gpio9 17:16 configuration for gpio8 15:14 configuration for gpio7 13:12 configuration for gpio6 11:10 configuration for gpio5 9:8 configuration for gpio4 7:6 configuration for gpio3 5:4 configuration for gpio2 3:2 configuration for gpio1 1:0 configuration for gpio0 do not copy free datasheet http://www.datasheet-pdf.com/
92 ? AR9223 single-chip 2x2 mimo mac/bb/radio for 802.11n wlans atheros communications, inc. 92 ? october 2009 company confidential 6.2.7 rtc interface registers rtc registers occupy the offset range 0x7000? 0x7ffc in the AR9223 address space. within this address range, the 0x7040?0x7058 registers are always on and available for software access regardless of whether the rtc is asleep. table 6-13 shows the register mapping. 6.2.7.1 rtc reset and force sleep and force wakeup (rtc_reset) offset: 0x7040 access: read/write default: 0 6.2.7.2 rtc sleep status (rtc_status) offset: 0x7044 access: read-only default: n/a 6.2.7.3 rtc force derived rtc and bypass derived rtc (rtc_derived) offset: 0x7048 access: read/write default: 0 table 6-13. rtc interface registers (always on) offset name description page 0x7040 rtc_reset rtc reset and force sleep and force wakeup page 92 0x7044 rtc_status rtc sleep status page 92 0x7048 rtc_derived rtc force derived rtc and bypass derived rtc page 92 0x704c rtc_force_wake rtc force wake page 93 0x7050 rtc_int_cause rtc interrupt cause page 93 0x7050 rtc_cause_clr rtc interrupt cause clear page 93 0x7054 rtc_int_enable rtc interrupt enable page 94 0x7058 rtc_int_mask rtc interrupt mask page 94 bit description 31:1 reserved 0 rtc reset (active low) bit description 31:6 reserved 5pll_changing si gnal from rtc 4 rtc cold reset (active high) 3 rtc in wakeup state 2 rtc in sleep state 1 rtc in on state 0 rtc in shutdown state bit description 31:2 reserved 1force derived rtc 0 bypass derived rtc do not copy free datasheet http://www.datasheet-pdf.com/
atheros communications, inc. AR9223 single-chip 2x2 mimo mac/bb/radio for 802.11n wlans ? 93 company confidential october 2009 ? 93 6.2.7.4 rtc force wake (rtc_force_wake) offset: 0x704c access: read/write default: 3 6.2.7.5 rtc interrupt cause (rtc_int_cause) offset: 0x7050 access: read-only default: 0 note: the rtc interrupt controller works the same way as the host interface interrupt controller. each bit in this interrupt cause register pertains to an event as described. 6.2.7.6 rtc interrupt cause clear (rtc_cause_clr) offset: 0x7050 access: write-only default: 0 note: a write of 1 to any bit in this register clears that bit in the ?rtc interrupt cause (rtc_int_cause)? register until the corresponding event reoccurs. bit description 31:2 reserved 1 0 do not assert force_wake on mac interrupt 1 assert force_wake on mac interrupt 0 force_wake signal to the mac bit description 31:6 reserved 5 pll_changing 4 software access of an rtc register when it is not in the on state 3 rtc in wakeup state 2 rtc in sleep state 1 rtc in on state 0 rtc in shutdown state bit description 31:6 reserved 5 writing 1 to this bit clears the pll_changing interrupt from the ?rtc interrupt cause (rtc_int_cause)? register. 4 writing 1 to this bit clears the software ac cess of an rtc register interrupt from the ?rtc interrupt cause (rtc_int_cause)? register. 3 writing 1 to this bit clears the rtc in wakeup state interrupt from the ?rtc interrupt cause (rtc_int_cause)? register. 2 writing 1 to this bit clears the rt c in sleep state interrupt from the ?rtc interrupt cause (rtc_int_cause)? register. 1 writing 1 to this bit clears the rt c in on state interrupt from the ?rtc interrupt cause (rtc_int_cause)? register. 0 writing 1 to this bit clears the rtc in shutdown state interrupt from the ?rtc interrupt cause (rtc_int_cause)? register. do not copy free datasheet http://www.datasheet-pdf.com/
94 ? AR9223 single-chip 2x2 mimo mac/bb/radio for 802.11n wlans atheros communications, inc. 94 ? october 2009 company confidential 6.2.7.7 rtc interrupt enable (rtc_int_enable) offset: 0x7054 access: read/write default: 0 note: writing a 1 to any bit in this register allows that bit in the ?rtc interrupt cause (rtc_int_cause)? register to be set when the corresponding event occurs. writing a 0 to any bit in this register automatically clears the corresponding bit in the interrupt cause register regardless of the corresponding event. 6.2.7.8 rtc interrupt mask (rtc_int_mask) offset: 0x7058 access: read/write default: 0 note: writing a 1 to any bit in this register allows the corresponding event to generate an rtc interrupt to the host interface which can in turn be programmed to generate a system interrupt. the corresponding bit in the ?rtc interrupt enable (rtc_int_enable)? register must also be set. bit description 31:6 reserved 5 0 clears the pll_changing bit in the ?rtc interrupt cause (rtc_int_cause)? . 1 allows the pll changing bit in the ?rtc interrupt cause (rtc_int_cause)? to be set when the corresponding event occurs. 4 0 clears the software access of an rtc register bit in the ?rtc interrupt cause (rtc_int_cause)? . 1 allows the software access of an rtc register bit in the ?rtc interrupt cause (rtc_int_cause)? to be set when the corresponding event occurs. 3 0 clears the rtc in wakeup state bit in the ?rtc interrupt cause (rtc_int_cause)? . 1 allows the rtc in wakeup state bit in the ?rtc interrupt cause (rtc_int_cause)? to be set when the corresponding event occurs. 2 0 clears the rtc in sleep state bit in the ?rtc interrupt cause (rtc_int_cause)? . 1 allows the rtc in sleep state bit in the ?rtc interrupt cause (rtc_int_cause)? to be set when the corresponding event occurs. 1 0 clears the rtc in on state bit in the ?rtc interrupt cause (rtc_int_cause)? . 1 allows the rtc in on state bit in the ?rtc interrupt cause (rtc_int_cause)? to be set when the corresponding event occurs. 0 0 clears the rtc in shutdown state bit in the ?rtc interrupt cause (rtc_int_cause)? . 1 allows the rtc in shutdown state bit in the ?rtc interrupt cause (rtc_int_cause)? to be set when the corresponding event occurs. bit description 31:6 reserved 5 writing 1 to this bit allows the corresponding pl l_changing event to generate an rtc interrupt to the host interface. 4 writing 1 to this bit allows the corresponding softwa re access of an rtc register event to generate an rtc interrupt to the host interface. 3 writing 1 to this bit allows the corresponding rtc in wakeup state event to generate an rtc interrupt to the host interface. 2 writing 1 to this bit allows the corresponding rtc in sleep state event to generate an rtc interrupt to the host interface. 1 writing 1 to this bit allows the corresponding rtc in on state event to generate an rtc interrupt to the host interface. 0 writing 1 to this bit allows th e corresponding rtc in shutdown state event to generate an rtc interrupt to the host interface. do not copy free datasheet http://www.datasheet-pdf.com/
atheros communications, inc. AR9223 single-chip 2x2 mimo mac/bb/radio for 802.11n wlans ? 95 company confidential october 2009 ? 95 6.2.8 mac pcu registers table 6-14 shows the mapping of these registers. table 6-14. mac pcu registers address name description page 0x08000 mac_pcu_sta_addr_l32 sta address lower 32 bits page 97 0x08004 mac_pcu_sta_addr_u16 sta address upper 16 bits page 97 0x08008 mac_pcu_bssid_l32 bssid lower 32 bits page 98 0x0800c mac_pcu_bssid_u16 bssid upper 16 bits page 98 0x08010 mac_pcu_bcn_rssi_ave beacon rssi average page 98 0x08014 mac_pcu_ack_cts_timeout ack and cts timeout page 98 0x08018 mac_pcu_bcn_rssi_ctl beacon rssi control page 99 0x0801c mac_pcu_usec_latency millisec ond counter and rx/tx latency page 99 0x08020 mac_pcu_rese t_tsf reset tsf page 99 0x08038 mac_pcu_max_cfp_dur maximum cfp duration page 100 0x0803c mac_pcu_rx_filter rx filter page 100 0x08040 mac_pcu_mcast_filter_l32 mult icast filter mask lower 32 bits page 100 0x08044 mac_pcu_mcast_filter_u32 mult icast filter mask upper 32 bits page 101 0x08048 mac_pcu_diag_sw diagnostic switches page 101 0x0804c mac_pcu_tsf_l32 tsf lower 32 bits page 102 0x08050 mac_pcu_tsf_u32 tsf upper 32 bits page 102 0x0805c mac_pcu_aes_mute_mask_0 aes mute mask 0 page 102 0x08060 mac_pcu_aes_mute_mask_1 aes mute mask 1 page 103 0x08080 mac_pcu_last_b eacon_tsf last rece ive beacon tsf page 103 0x08084 mac_pcu_nav current nav page 103 0x08088 mac_pcu_rts_success_c nt successful rts count page 103 0x0808c mac_pcu_rts_fail_cnt failed rts count page 104 0x08090 mac_pcu_ack_fail_cnt fail ack count page 104 0x08094 mac_pcu_fcs_fail_cnt failed fcs count page 104 0x08098 mac_pcu_beacon_cnt beacon count page 104 0x080d4 mac_pcu_slp1 sleep 1 page 105 0x080d8 mac_pcu_slp2 sleep 2 page 105 0x080e0 mac_pcu_addr1_mask_l32 address 1 mask lower 32 bits page 105 0x080e4 mac_pcu_addr1_mask_u16 a ddress 1 mask upper 16 bits page 105 0x080e8 mac_pcu_tpc tx power control page 106 0x080ec mac_pcu_tx_frame_cnt tx frame counter page 106 0x080f0 mac_pcu_rx_frame_cnt rx frame counter page 106 0x080f4 mac_pcu_rx_clear_cnt rx clear counter page 106 0x080f8 mac_pcu_cycle_ cnt cycle counter page 106 0x080fc mac_pcu_quiet_time_1 quiet time 1 page 107 0x08100 mac_pcu_quiet_time_2 quiet time 2 page 107 do not copy free datasheet http://www.datasheet-pdf.com/
96 ? AR9223 single-chip 2x2 mimo mac/bb/radio for 802.11n wlans atheros communications, inc. 96 ? october 2009 company confidential 0x08108 mac_pcu_qos_no_ack qos no ack page 107 0x0810c mac_pcu_phy_error_mask phy error mask page 108 0x08114 mac_pcu_rxbuf_threshold rx buffer threshold page 108 0x08118 mac_pcu_mic_qos_control qos control page 109 0x0811c mac_pcu_mic_qos_select michael qos select page 109 0x08120 mac_pcu_misc_mode miscellaneous mode page 109 0x08124 mac_pcu_filter_ofdm_cnt filtered ofdm counter page 111 0x08128 mac_pcu_filter_cck_c nt filtered cck counter page 111 0x0812c mac_pcu_phy_err_cnt_1 phy error counter 1 page 111 0x08130 mac_pcu_phy_err_cnt_1_mask phy error counter 1 mask page 112 0x08134 mac_pcu_phy_err_cnt_2 phy error counter 2 page 112 0x08138 mac_pcu_phy_err_cnt_2_mask phy error counter 2 mask page 112 0x0813c mac_pcu_tsf_threshold tsf threshold page 113 0x08144 mac_pcu_phy_error_eifs _mask phy error eifs mask page 113 0x08168 mac_pcu_phy_err_cnt_3 phy error counter 3 page 113 0x0816c mac_pcu_phy_err_cnt_3_mask phy error counter 3 mask page 113 0x08178 mac_pcu_hcf_timeout hcf timeout page 114 0x081d0 mac_pcu_txsif s sifs, tx latency and ack shift page 114 0x081ec mac_pcu_txop_x txop for non-qos frames page 114 0x081f0 mac_pcu_txop_0_3 txop for tid 0 to 3 page 115 0x081f4 mac_pcu_txop_4_7 txop for tid 4 to 7 page 115 0x081f8 mac_pcu_txop_8_11 txop for tid 8 to 11 page 115 0x081fc mac_pcu_txop_12_15 txop for tid 0 to 3 page 115 0x08200 mac_pcu_generic_time rs[0:15] generic timers page 116 0x08240 mac_pcu_generic_timers _mode generic timers mode page 116 0x08244 mac_pcu_slp32_mode 32 khz sleep mode page 116 0x08248 mac_pcu_slp32_wake 32 khz sleep wake page 117 0x0824c mac_pcu_slp32_inc 32 khz sleep increment page 117 0x08250 mac_pcu_slp_mib1 sl eep mib sleep count page 117 0x08254 mac_pcu_slp_mib2 sl eep mib cycle count page 117 0x08258 mac_pcu_slp_mib3 sleep mib control status page 118 0x08318 mac_pcu_20_40_mode global mode page 118 0x08328 mac_pcu_rx_clear_diff_cnt d ifference rx_clear counter page 118 0x08330 mac_pcu_ba_bar_control cont rol registers for block ba control fields page 119 0x08334 mac_pcu_legacy_plcp_ spoof legacy plcp spoof page 119 0x08338 mac_pcu_phy_error_mask_cont p hy error mask and eifs mask page 119 0x0833c mac_pcu_tx_timer tx timer page 120 0x08800 mac_pcu_key_cache[0:1023] key cache lower half page 120 table 6-14. mac pcu registers address name description page do not copy free datasheet http://www.datasheet-pdf.com/
atheros communications, inc. AR9223 single-chip 2x2 mimo mac/bb/radio for 802.11n wlans ? 97 company confidential october 2009 ? 97 6.2.8.1 sta address lower 32 bits (mac_pcu_sta_addr_l32) this register contains the lower 32 bits of the sta address. offset: 0x08000 access: hardware = read-only software = read/write reset value: 0x0 6.2.8.2 sta address upper 16 bits (mac_pcu_sta_addr_u16) this register contains the lower 32 bits of the sta address. offset: 0x08004 access: hardware = read-only software = read/write reset value: 0x2000_0000 bit name description 31:0 addr_31_0 lower 32 bits of sta mac address (pcu_sta_addr[31:0]) bit name description 15:0 pcu_sta_addr[47:32] upper 16 bi ts of station mac address 16 pcu_ap set if sta is an ap 17 pcu_adhoc set if sta is in an ad hoc network 18 pcu_psmode set if sta is in power-save mode 19 pcu_no_keysearch disable key search 20 pcu_pcf set if associated ap is pcf capable 23:21 res reserved 24 pcu_ackcts_6mb use 6 mbps rate for ack and cts 25 pcu_bsrate_11b 802.11b base rate 0 use all rates 1 use only 1?2 mbps 26 res reserved 27 reg_crpt_mic_enable enabl es the checking and insertion of mic in tkip 28 pcu_ksrch_mode search key cache first. if n ot, match use offset for iv = 0, 1, 2, 3. if ksrch_mode = 0 then do not search if iv = 1, 2, or 3, then search if iv = 0, do not search 29 reg_preserve_seqnum stops pcu from replacing the sequence number; must be set to 1 30 pcu_cbciv_endian endianess of iv in cbc nonce 31 reg_adhoc_mcast_search enables the key cache search for ad hoc mcast packets do not copy free datasheet http://www.datasheet-pdf.com/
98 ? AR9223 single-chip 2x2 mimo mac/bb/radio for 802.11n wlans atheros communications, inc. 98 ? october 2009 company confidential 6.2.8.3 bssid lower 32 bits (mac_pcu_bssid_l32) offset: 0x08008 access: hardware = read/write software = read/write reset value: 0x0 this register contains the lower 32 bits of the bss identification information. 6.2.8.4 bssid upper 16 bits (mac_pcu_bssid_u16) offset: 0x0800c access: hardware = read/write software = read/write reset value: 0x0 this register contains th e upper 32 bits of the bss identification information. 6.2.8.5 beacon rssi average (mac_pcu_bcn_rssi_ave) offset: 0x08010 access: hardware = read/write software = read-only reset value: 0x800 bcn_rssi_ave 6.2.8.6 ack and cts timeout (mac_pcu_ack_cts_timeout) offset: 0x08014 access: hardware = read-only software = read/write reset value: 0x0 bit name description 31:0 pcu_bssid[31:0] lowe r 32 bits of bssid bit name description 15:0 pcu_bssid[47:32] upper 16 bits of bssid 26:16 pcu_aid association id 31:17 res reserved bit name description 11:0 reg_bcn_rssi_ave holds the average rssi with 1/16 db resolution. the rssi is averaged over multiple beacons which matched our bssid. ave_value is 12 bits with 4 bits belo w the normal 8 bits. these lowest 4 bits provide for a resolution of 1/16 db. the averaging function is depends on the bcn_rssi_weight; determines the ratio of weight given to the current rssi value compared to the average accumulated value. 31:12 res reserved bit name description 13:0 pcu_ack_timeout timeout whil e waiting for ack (in cycles) 29:16 pcu_cts_timeout timeout whil e waiting for cts (in cycles) 31:30 res reserved do not copy free datasheet http://www.datasheet-pdf.com/
atheros communications, inc. AR9223 single-chip 2x2 mimo mac/bb/radio for 802.11n wlans ? 99 company confidential october 2009 ? 99 6.2.8.7 beacon rssi control (mac_pcu_bcn_rssi_ctl) offset: 0x08018 access: hardware = read-only software = read/write reset value: 0x0 6.2.9 ms counter and rx/tx la tency (mac_pcu_usec_latency) offset: 0x0801c access: hardware = read-only software = read/write reset value: 0x0 6.2.9.8 reset tsf (mac_pcu_reset_tsf) offset: 0x08020 access: hardware = read/write software = read/write reset value: 0x0 controls beacon operation by the pcu. bit name description 7:0 pcu_rssi_thr the threshold at which the beacon low rssi interrupt is asserted when the average rssi ( ?bcn_rssi_ave? ) below this level 15:8 pcu_bcn_miss_thr threshold at which the beacon miss interrupt asserts. because the beacon miss counter increments at tbtt, it in crements to 1 before the first beacon. 28:24 reg_bcn_rssi_weight used to calculate ?bcn_rssi_ave? 29 reg_bcn_rssi_rst_ strobe the bcn_rssi_reset clears ?bcn_rssi_ave? to aid in changing channels 31:30 res reserved bit name description 6:0 res reserved 22:14 pcu_txdelay baseband tx latency to start of timestamp in beacon frame (in s) 28:23 pcu_rxdelay baseband rx late ncy to start of signal (in s) 31:29 res reserved bit name description 23:0 res reserved 24 one_shot setting this bit caus es the tsf to reset. this register clears immediately after being reset. 31:25 res reserved do not copy free datasheet http://www.datasheet-pdf.com/
100 ? AR9223 single-chip 2x2 mimo mac/bb/radio for 802.11n wlans atheros communications, inc. 100 ? october 2009 company confidential 6.2.9.9 maximum cfp duration (mac_pcu_max_cfp_dur) offset: 0x08038 access: hardware = read-only software = read/write reset value: 0x0 contains the maximum time for a cfp. 6.2.9.10 rx filter (mac_pcu_rx_filter) offset: 0x0803c access: hardware = read-only software = read/write reset value: 0x0 this register determines rx frame filtering. note: if any bit is set, the corresponding packet types pass the filter and are dmaed. all filter conditions except the promiscuous setting rely on the no early phy error and protocol version being checked to ensure it is version 0. 6.2.9.11 multicast filter mask lower 32 bits (mac_pcu_mcast_filter_l32) offset: 0x08040 access: hardware = read-only software = read/write reset value: 0x0 this register contains the lower 32 bits of the multicast filter mask. bit name description 15:0 pcu_max_cfpdur maximum contenti on free period duration (in s) 31:16 res reserved bit name description 0 unicast unicast frame enable enable reception of unicast (directed) frames that match the sta address 0 disable. no ack will return 1enable 1 multicast multicast frame enable enable reception of multicast fram es that match the multicast filter 2 broadcast broadcast frame enable enable reception of non beacon broadc ast frames that originate from the bss whose id matches bssid 3 control control frame enable enable reception of control frames 4 beacon beacon frame enable enable reception of beacon frames. 5 promiscuous promiscuous receive enable enable reception of all frames, including errors 6r e sr e s e r v e d 7 probe_req probe request enable. enables reception of all probe request frames 8r e sr e s e r v e d 9 my_beacon retrieves any beacon frame with matching ssid 13:10 res reserved 14 ps_poll enables receipt of ps-poll 15 mcast_bcast_all enables receipt of all multicast and broadcast frames 31:10 res reserved bit name description 31:0 pcu_mcast_mask multicast fi lter mask low. lower 32 bits of multicast filter mask. do not copy free datasheet http://www.datasheet-pdf.com/
atheros communications, inc. AR9223 single-chip 2x2 mimo mac/bb/radio for 802.11n wlans ? 101 company confidential october 2009 ? 101 6.2.9.12 multicast filter mask upper 32 bits (mac_pcu_mcast_filter_u32) offset: 0x08044 access: hardware = read-only software = read/write reset value: 0x0 this register contains th e upper 32 bits of the multicast filter mask. 6.2.9.13 diagnostic switches (mac_pcu_diag_sw) offset: 0x08048 access: hardware = read-only software = read/write reset value: 0x0 controls the operation of the pcu, including enabling/disabling acknowledgements, cts, transmission, reception, encryption, loopback, fcs, channel information, and scrambler seeds. bit name description 31:0 pcu_mcast_mask multicast fi lter mask high. upper 32 bits of multicast filter mask. bit name description 0 pcu_invalkey_noack enable or disable acknowledgement when a valid key is not found for the received frames in the key cache. 1 no_ack enable or disable acknowle dgement generation for all frames 2 no_cts enable or disable cts generation 3 no_encrypt enable or disable encryption 4 no_decrypt enable or disable decryption 5 halt_rx enable or disable reception 6 loop_back enable or disable tx data loopback 7 corrupt_fcs enable or disable corrupt fcs. enabling this bit causes an invalid fcs to be appended to a fr ame during transmission. 16:8 res reserved 17 accept_non_v0 enable or disable protocol field 19:18 res reserved 20 rx_clear_high force rx_clear high 21 ignore_nav ignore virtual carrier sense (nav) 22 chan_idle_high force channel idle high 23 phyerr_enable_eifs_ctl uses fram ed and wait_wep in the pcu_rx_err logic if bits is set to 0 24 res reserved 25 force_rx_abort force rx abort bit in conj unction with rx block aids quick channel change to shut down rx. the force rx abort bit kills with the rx_abort any frame currently transferring between the mac and baseband. while the rx block bit prevents an y new frames from getting started. 26 saturate_cycle_cnt the saturate cycl e count bit, if set, causes the ?cycle counter (mac_pcu_cycle_cnt)? register to saturate instead of shifting to the right by 1 every time the coun t reaches 0xffffffff. this saturate condition also holds the rx_clear , rx_frame, and tx_frame counts. 27 res reserved 28 rx_clear_ctl_low force the rx _clear_ctl signal to appear to the mac as being low 29 rx_clear_ext_low force the rx_clear_ext signal to appear to the mac as being low 31:30 res reserved do not copy free datasheet http://www.datasheet-pdf.com/
102 ? AR9223 single-chip 2x2 mimo mac/bb/radio for 802.11n wlans atheros communications, inc. 102 ? october 2009 company confidential 6.2.9.14 tsf lower 32 bits (mac_pcu_tsf_l32) offset: 0x0804c access: hardware = read/write software = read/write reset value: 0xfffffff 6.2.9.15 tsf upper 32 bits (mac_pcu_tsf_u32) offset: 0x08050 access: hardware = read/write software = read/write reset value: 0xfffffff 6.2.9.16 aes mute mask 0 (mac_pcu_aes_mute_mask_0) offset: 0x0805c access: hardware = read-only software = read/write reset value: 0xc7ff 6.2.9.17 aes mute mask 1(mac_pcu_aes_mute_mask_1) offset: 0x08060 access: hardware = read-only software = read/write reset value: 0x000f bit name description 31:0 value the timestamp value in s. writes to this register do not cause the tsf to change. rather, the value is held in a temporary staging area until this register is written, at which point both the lower and upper pa rts of the tsf are loaded. a read result of 0xffffffff indicates that the read occurred before tsf logic came out of sleep. it may take up to 45 s after the chip is brought out of sleep for the tsf logic to wake. bit name description 31:0 value the timestamp value in s bit name description 15:0 fc_mutemask aes mute mask for frame control field 31:16 qos_mutemask aes mute mask for tid field bit name description 15:0 seq_mutemask aes mute mask for sequence number field 31:16 fc)mgmt aes mute mask for management frame control field do not copy free datasheet http://www.datasheet-pdf.com/
atheros communications, inc. AR9223 single-chip 2x2 mimo mac/bb/radio for 802.11n wlans ? 103 company confidential october 2009 ? 103 6.2.9.18 last rx beacon tsf (mac_pcu_last_beacon_tsf) offset: 0x08080 access: hardware = write-only software = read-only reset value: 0x0 this threshold register indicates the minimum amount of data required before initiating a transmission. 6.2.9.19 current nav (mac_pcu_nav) offset: 0x08084 access: hardware = read/write software = read/write reset value: 0x0 6.2.9.20 successful rts count (mac_pcu_rts_success_cnt) offset: 0x08088 access: hardware = read/write software = read-only reset value: 0x0 this register counts the number of successful rts exchanges. the counter stops at 0xffff. after a read, automatically resets to 0. bit name description 31:0 last_tstp beacon timestamp. lower 32 bits of timestamp of the last beacon received. bit name description 25:0 cs_nav current nav value (in s) 31:26 res reserved bit name description 15:0 rts_ok rts/cts exchange success counter 31:16 res reserved do not copy free datasheet http://www.datasheet-pdf.com/
104 ? AR9223 single-chip 2x2 mimo mac/bb/radio for 802.11n wlans atheros communications, inc. 104 ? october 2009 company confidential 6.2.9.21 failed rts count (mac_pcu_rts_fail_cnt) offset: 0x0808c access: hardware = read/write software = read-only reset value: 0x0 this register counts the number of failed rts exchanges. the counter stops at 0xffff. after a read, this register is automatically reset to 0. 6.2.9.22 fail ack count (mac_pcu_ack_fail_cnt) offset: 0x08090 access: hardware = read/write software = read-only reset value: 0x0 this register counts the number of failed acknowledgements. the counter stops at 0xffff. after a read, this register is automatically reset to 0. 6.2.9.23 failed fcs count (mac_pcu_fcs_fail_cnt) offset: 0x08094 access: hardware = read/write software = read-only reset value: 0x0 this register counts the number of failed frame check sequences. the co unter stops at 0xffff. after a read, this register is automatically reset to 0. 6.2.9.24 beacon count (mac_pcu_beacon_cnt) offset: 0x08098 access: hardware = read/write software = read-only reset value: 0x0 this register counts the number of valid beacon frames received. the counter stops at 0xffff. after a read, automatically resets to 0. bit name description 15:0 rts_fail rts/cts exchange failure counter 31:16 res reserved bit name description 15:0 ack_fail data/ack failure counter 31:16 res reserved bit name description 15:0 fcs_fail fcs failure counter 31:16 res reserved bit name description 15:0 beaconcnt valid beacon counter 31:16 res reserved do not copy free datasheet http://www.datasheet-pdf.com/
atheros communications, inc. AR9223 single-chip 2x2 mimo mac/bb/radio for 802.11n wlans ? 105 company confidential october 2009 ? 105 6.2.9.25 sleep 1 (mac_pcu_slp1) offset: 0x080d4 access: hardware = read/write software = read-only reset value: 0x0 the sleep 1 register in conjunction with the ?sleep 2 (mac_pcu_slp2)? register, controls when the AR9223 should wake when waiting for ap rx traffic. sleep registers are only used when the AR9223 is in sta mode. 6.2.9.26 sleep 2 (mac_pcu_slp2) offset: 0x080d8 access: hardware = read/write software = read-only reset value: 0x0 6.2.9.27 address 1 mask lower 32 bits (mac_pcu_addr1_mask_l32) offset: 0x080e0 access: hardware = read-only software = read/write reset value: 0xffffffff this sta register provides multiple bssid support when the AR9223 is in ap mode. 6.2.9.28 address 1 mask upper 16 bits (mac_pcu_addr1_mask_u16) offset: 0x080e4 access: hardware = read-only software = read/write reset value: 0xffff this sta register provides multiple bssid support when the AR9223 is in ap mode. bit name description 18:0 res reserved 19 assume_dtim a mode bit which indicates whet her to assume a beacon was missed when the slp_beacon_timeout occurs with no received beacons, in which case is assumes the dtim was missed, and waits for cab. 20 res reserved 31:21 cab_timeout time in tu that the pcu waits for cab after receiving the beacon or the previous cab, insuring that if no cab is received after the beacon is received or if a long gap occurs between cabs, the cab po wersave state returns to idle. bit name description 20:0 res reserved 31:21 beacon_timeout time in tu that the pcu waits for a beacon after waking up. if this time expires, the pcu woke due to slp_next_dtim, and slp_assume_dtim is active, then it assumes the beacon was missed and goes directly to watching for cab. otherwise when this time expires, the beacon powersave state returns to idle. bit name description 31:0 sta_mask_l sta address mask lower 32-bit register. provides multiple bssid support. bit name description 31:0 sta_mask_l sta address mask upper 16-bit register. provides multiple bssid support. do not copy free datasheet http://www.datasheet-pdf.com/
106 ? AR9223 single-chip 2x2 mimo mac/bb/radio for 802.11n wlans atheros communications, inc. 106 ? october 2009 company confidential 6.2.9.29 tx power control (mac_pcu_tpc) offset: 0x080e8 access: hardware = read-only software = read/write reset value: 0x003f_3f3f this register set the transmit power for self- generated response frames. 6.2.9.30 tx frame counter (mac_pcu_tx_frame_cnt) offset: 0x080ec access: hardware = read/write software = read/write reset value: 0x0 the tx frame counter counts the number of cycles the tx_frame signal is active. 6.2.9.31 rx frame counter (mac_pcu_rx_frame_cnt) offset: 0x080f0 access: hardware = read/write software = read/write reset value: 0x0 the receive frame counter counts the number of cycles the rx_frame signal is active. 6.2.9.32 rx clear counter (mac_pcu_rx_clear_cnt) offset: 0x080f4 access: hardware = read/write software = read/write reset value: 0x0 the receive clear counter counts the number of cycles the rx_clear signal is not active. 6.2.9.33 cycle counter (mac_pcu_cycle_cnt) offset: 0x080f8 access: hardware = read/write software = read/write reset value: 0x0 the cycle counter counts the number of clock cycles. bit name description 5:0 ack_pwr ack self-generated response frames 7:6 res reserved 13:8 cts_pwr cts self-generated response frames 15:14 res reserved 21:16 chirp_pwr chirp self-generated response frames 31:22 res reserved bit name description 31:0 tx_frame_cnt counts the number of cy cles the tx_frame signal is active bit name description 31:0 rx_frame_cnt counts the number of cy cles the rx_frame signal is active bit name description 31:0 rx_clear_cnt counts the number of cycles the rx_clear signal is low bit name description 31:0 cycle_cnt counts the number of clock cycles do not copy free datasheet http://www.datasheet-pdf.com/
atheros communications, inc. AR9223 single-chip 2x2 mimo mac/bb/radio for 802.11n wlans ? 107 company confidential october 2009 ? 107 6.2.9.34 quiet time 1 (mac_pcu_quiet_time_1) offset: 0x080fc access: hardware = read-only software = read/write reset value: 0x0 the quiet time register s implement the quiet time function specified in the proposed 802.11h extension supporting radar detection. 6.2.9.35 quiet time 2 (mac_pcu_quiet_time_2) offset: 0x080fc access: hardware = read-only software = read/write reset value: 0x0 the quiet time registers implement the quiet time function specified in the proposed 802.11h extension supporting radar detection. note: quiet_enable is implemented as generic_timer_enable and next_quiet as generic_timer_next. quiet_period is implemented as generic_timer_period. 6.2.9.36 qos no ack (mac_pcu_qos_no_ack) offset: 0x08108 access: hardware = read-only software = read/write reset value: 0x52 this register provides a mechanism to locate the noack information in the qos field and determine which encoding means noack. bit name description 16:0 res reserved 17 quiet_ack_cts_enable if set, then the mac sends an ack or cts in response to a received frame 31:18 res reserved bit name description 15:0 res reserved 31:16 quiet_duration the length of time in tu s that the chip is required to be quiet bit name description 3:0 noack_2_bit_values these values are of a two bit field that indicate no ack noack_2_bit_value encoding matching no ack xxx1 00 xx1x 01 x1xx 10 1xxx 11 6:4 noack_bit_offset offsets from the byte where the no ack information should be stored; offset can range from 0 to 6 only 8:7 noack_byte_offset number of bytes from the byte after end of the header of a data packet to the byte location where no ack information is stored. (the end of the header is at byte offset 25 for 3-address packets and 31 for 4-address packets.) 31:9 res reserved do not copy free datasheet http://www.datasheet-pdf.com/
108 ? AR9223 single-chip 2x2 mimo mac/bb/radio for 802.11n wlans atheros communications, inc. 108 ? october 2009 company confidential 6.2.9.37 phy error mask (mac_pcu_phy_error_mask) offset: 0x0810c access: hardware = read-only software = read/write reset value: 0x2 note: provides the ability to choose which phy errors from the baseband to filter. the error number offsets into this register. if the mask value at the offset is 0, this error filters and does not show up on the rx queue. 6.2.9.38 rx buffer threshold (mac_pcu_rxbuf_threshold) offset: 0x08114 access: hardware = read-only software = read/write reset value: 0x400 bit name description 0 error transmit_underrun t ransmit underrun error 3:1 res reserved 4 error panic panic error 5 error radar_detect radar detect error 6 error abort abort error 7 error tx_interrupt_rx transmit interrupt 16:8 res reserved 17 error ofdm timing false detection for ofdm 18 error ofdm signal_parity ofdm signal parity error 19 error ofdm rate_illegal ofdm illegal rate error 20 error ofdm length_illegal ofdm illegal length error 21 error ofdm power_drop ofdm power drop error 22 error ofdm service ofdm service error 23 error ofdm restart ofdm restart error 24 res reserved 25 error cck timing false detection for cck 26 error cck header_crc cck crc header error 27 error cck rate_illegal cck illegal rate error 29:28 res reserved 30 error cck service cck service error 31 error cck restart cck restart error bit name description 10:0 rxbuf_thrshd when the number of valid entries in th e rx buffer is larger th an this threshold, host interface logic gives higher priority to the rx side to prevent rx buffer overflow. 31:11 res reserved do not copy free datasheet http://www.datasheet-pdf.com/
atheros communications, inc. AR9223 single-chip 2x2 mimo mac/bb/radio for 802.11n wlans ? 109 company confidential october 2009 ? 109 6.2.9.39 qos control (mac_pcu_mic_qos_control) offset: 0x08118 access: hardware = read-only software = read/write reset value: 0xaa 6.2.9.40 michael qos select (mac_pcu_mic_qos_select) offset: 0x0811c access: hardware = read-only software = read/write reset value: 0x3210 6.2.9.41 miscellaneous mode (mac_pcu_misc_mode) bit name description 1:0 mic_qos_control [0] mic qos control [0] 0 use 0 when calculating michael 1 use 1 when calculating michael 2 use mic_qos_select when calculating michael 3 use inverse of mic_qos_select when calculating michael 3:2 mic_qos_control [1] mic qos control [1]. see options for ?mic_qos_control [0]? . 5:4 mic_qos_control [2] mic qos control [2]. see options for ?mic_qos_control [0]? . 7:6 mic_qos_control [3] mic qos control [3]. see options for ?mic_qos_control [0]? . 9:8 mic_qos_control [4] mic qos control [4]. see options for ?mic_qos_control [0]? . 11:10 mic_qos_control [5] mic qos control [5]. see options for ?mic_qos_control [0]? . 13:12 mic_qos_control [6] mic qos control [6]. see options for ?mic_qos_control [0]? . 15:14 mic_qos_control [7] mic qos control [7]. see options for ?mic_qos_control [0]? . 16 mic_qos_enable enable mic qos control 0 disable hardware michael 1 enable hardware michael 31:17 res reserved bit name description 3:0 mic_qos_select [0] mic qos select [0]. sele ct the oos tid bit when calculating michael. 7:4 mic_qos_select [1] mic qos select [1]. sele ct the oos tid bit when calculating michael. 11:8 mic_qos_select [2] mic qos select [2]. sele ct the oos tid bit when calculating michael. 15:12 mic_qos_select [3] mic qos select [3]. sele ct the oos tid bit when calculating michael. 19:16 mic_qos_select [4] mic qos select [4]. sele ct the oos tid bit when calculating michael. 23:20 mic_qos_select [5] mic qos select [5]. sele ct the oos tid bit when calculating michael. 27:24 mic_qos_select [6] mic qos select [6]. sele ct the oos tid bit when calculating michael. 31:28 mic_qos_select [7] mic qos select [7]. sele ct the oos tid bit when calculating michael. do not copy free datasheet http://www.datasheet-pdf.com/
110 ? AR9223 single-chip 2x2 mimo mac/bb/radio for 802.11n wlans atheros communications, inc. 110 ? october 2009 company confidential offset: 0x08120 access: hardware = read-only software = read/write reset value: 0x8f24800 bit name description 0 bssid_match_for ce if the bssid_match_force bit is set, all logic based on matching the bssid thinks that the bssid matches. 1r e sr e s e r v e d 2 mic_new_ location_enable if mic_new_location_enable is set, the tx michael key is assumed to be co-located in the same entry th at the rx michael key is located. 3 tx_add_tsf if the tx_add_tsf bit is set, the ts f in the transmit packet will be added to the internal tsf value for transmit beacons and prob_response frames. 4 cck_sifs_mode if the cck_sifs_mode is set, the chip assumes that it is using 802.11g mode where sifs is set to 10 s and non-cck frames must add 6 to sifs to make it cck frames. this bit is n eeded in the duration calculation, which also needs the sifs_time register. 11:5 res reserved 12 txop_tbtt_limit_ enable if this limit is set, then logic to limit the value of the duration to fit the time remaining in txop and time remaining until tbtt is turned on. this logic will also filter frames, wh ich will exceed txop. 17:13 res reserved 18 force_quiet_ collision if the force_quiet_collision bit is set, the pcu thinks that it is in quiet collision period, kills any transmit fr ame in progress, and prevents any new frame from starting. 20:19 res reserved 21 tbtt_protect if the tbtt_protect bit is set, then the time from tbtt to 20 s after tbtt is protected from transmit. turn this off in ad hoc mode or if this mac is used in the ap. 22 hcf_poll _cancels_nav if the hcf_poll_cancels_nav bit is set when a directed hcf poll is received, the current nav is cancelled and hcf data burst can proceed at sifs. 23 rx_hcf_poll _enable if the rx_hcf_poll_enable bit is set, then the mac is enabled to receive directed hcf polls. if this bit is not set the receive state machine does not tell the rest of the mac that it has received a directed hcf poll. 24 clear_vmf if the clear_vmf bit is set, then the vmf mode in the transmit state machine will be cleared. set this bit to enter fa st channel change mode and clear it once fast channel change is over. 25 clear_first_hcf if the clear_first_hcf bit is set, then the first_hcf state will be cleared. set this bit to enter fast channel change mo de and clear the bit once fast channel change is over. 26 clear_ba_valid if the clear_ba_valid bit is set, the state of the block ack storage is invalidated. 27 sel_evm if the sel_evm bit is set, the evm fiel d of the rx descriptor status contains the evm data received from the baseband. if th is bit is cleared, the evm field of the rx descriptor status contains 3 bytes of legacy plcp, 2 service bytes, and 6 bytes of hp plcp. 28 always_perform _ key_search if this bit is set, key search is performe d for every frame in an aggregate. if this bit is cleared, key search is only perfor med for the first frame of an aggregate. unless the transmitter addres s is different between the frames in an aggregate. this bit has no effect on non-aggregate frame packets. 31:29 res reserved do not copy free datasheet http://www.datasheet-pdf.com/
atheros communications, inc. AR9223 single-chip 2x2 mimo mac/bb/radio for 802.11n wlans ? 111 company confidential october 2009 ? 111 6.2.9.42 filtered ofdm counter (mac_pcu_filter_ofdm_cnt) offset: 0x08124 access: hardware = read/write software = read/write reset value: 0x0 the filtered ofdm counters use the mib control signals. 6.2.9.43 filtered cck counter (mac_pcu_filter_cck_cnt) offset: 0x08128 access: hardware = read/write software = read/write reset value: 0x0 6.2.9.44 phy error counter 1 (mac_pcu_phy_err_cnt_1) offset: 0x0812c access: hardware = read/write software = read/write reset value: 0x0 the phy error counters count any phy error matching the respective mask. the bits of 32-bit masks correspond to the first 32 encoded values of the error. setting multiple bits in the mask provides an oring function to provide flexibility in counting. for example, if setting the mask bits to 0xff0000ff, then all phy errors from 0?7 and 24?31 are counted. bit name description 23:0 filtofdm_cnt counts the ofdm frames that were filtered using mib control signals. the mib freeze register holds all the values of these registers, and mib zeros out all the values of these registers. pib mib forces incrementation of all registers in each cycle. this counter saturates at the highest value and is writable. if the upper two bits of these counters are b11, pcu_mib_thre shold is asserted and an interrupt generated. 31:24 res reserved bit name description 23:0 filtcck_cnt counts the cck frames that were filtered using mib control signals. the mib freeze register holds all the values of these registers, and mib zeros out all the values of these registers. pib mib forces incrementation of all registers in each cycle. this counter saturates at the highest value and is writable. if the upper two bits of these counters are b11, pcu_mib_thre shold is asserted and an interrupt generated. 31:24 res reserved bit name description 23:0 phy_error_cnt1 counts any phy er ror1 using mib control signals. the mib freeze register holds all the valu es of these registers, and mib zeros out all the values of these registers. pib mib forces incrementation of all registers in each cycle. counter saturates at the highest value an d is writable. if the upper two counter bits are b11, pcu_mib_threshold is asserted and an interrupt generated. 31:24 res reserved do not copy free datasheet http://www.datasheet-pdf.com/
112 ? AR9223 single-chip 2x2 mimo mac/bb/radio for 802.11n wlans atheros communications, inc. 112 ? october 2009 company confidential 6.2.9.45 phy error counter 1 mask (mac_pcu_phy_err_cnt_1_mask) offset: 0x08130 access: hardware = read-only software = read/write reset value: 0x0 6.2.9.46 phy error counter 2 (mac_pcu_phy_err_cnt_2) offset: 0x08134 access: hardware = read-only software = read/write reset value: 0x0 6.2.9.47 phy error counter 2 mask (mac_pcu_phy_err_cnt_2_mask) offset: 0x08138 access: hardware = read-only software = read/write reset value: 0x0 bit name description 31:0 phy_error_cnt_mask1 counts any error that matches the phy error1 mask. the values of any 32-bit masks co rrespond to the first 32 encoded values of the error. setting multiple bits in the mask provides an oring function to allow counting flexib ility (e.g., setting the mask to 0xff0000ff means all phy errors from 0:7 and 24:31 are counted). bit name description 23:0 phy_error_cnt counts any error th at matches the phy error2 mask. the values of any 32-bit masks co rrespond to the first 32 encoded values of the error. setting multiple bits in the mask provides an oring function to allow counting flexib ility (e.g., setting the mask to 0xff0000ff means all phy errors from 0:7 and 24:31 are counted). 31:24 res reserved bit name description 31:0 phy_error_cnt_mask2 counts any phy error2 using mib control signals. the mib freeze register holds all the values of these registers, and mib zeros out all the values of th ese registers. pib mib forces incrementation of all registers in each cycle. this counter saturates at the highest value and is writable. if the upper two bits of these counters are b11, pcu_mib_threshold is asserted and an interrupt generated. do not copy free datasheet http://www.datasheet-pdf.com/
atheros communications, inc. AR9223 single-chip 2x2 mimo mac/bb/radio for 802.11n wlans ? 113 company confidential october 2009 ? 113 6.2.9.48 tsf threshold (mac_pcu_tsf_threshold) offset: 0x0813c access: hardware = read-only software = read/write reset value: 0x0 6.2.9.49 phy error eifs mask (mac_pcu_phy_error_eifs_mask) offset: 0x08144 access: hardware = read-only software = read/write reset value: 0x0 6.2.9.50 phy error counter 3 (mac_pcu_phy_err_cnt_3) offset: 0x08168 access: hardware = read-only software = read/write reset value: 0x0 6.2.9.51 phy error counter 3 mask (mac_pcu_phy_err_cnt_3_mask) offset: 0x0816c access: hardware = read-only software = read/write reset value: 0x0 bit name description 15:0 tsf_threshold asserts the pcu_tsf_out_of_ran ge_inter if the corrected receive tsf in a beacon is different from the intern al tsf by more than this threshold. 31:16 res reserved bit name description 31:0 value this mask provides the ability to ch oose which phy errors from the baseband cause eifs delay. the error number is used as an offset into this mask. if the mask value at the offset is 1, then this error will not cause eifs delay. bit name description 23:0 phy_error_cnt3 count of phy errors that pass the phy_err_cnt_3_mask filter 31:24 res reserved bit name description 31:0 phy_error_cnt_ mask3 mask of the phy error number allowed to be counted do not copy free datasheet http://www.datasheet-pdf.com/
114 ? AR9223 single-chip 2x2 mimo mac/bb/radio for 802.11n wlans atheros communications, inc. 114 ? october 2009 company confidential 6.2.9.52 hcf timeout (mac_pcu_hcf_timeout) offset: 0x08178 access: hardware = read-only software = read/write reset value: 0x0 6.2.9.53 sifs, tx latency and ack shift (mac_pcu_txsifs) offset: 0x081d0 access: hardware = read-only software = read/write reset value: 0x0 6.2.9.54 txop for non-qos frames (mac_pcu_txop_x) offset: 0x081ec access: hardware = read-only software = read/write reset value: 0x0 bit name description 15:0 value the time the pcu waits after the hcf trigger timer occu rs before the pcu returns to sleep mode, unless the hcf po ll has been detected. an interrupt is generated if the timeout occurs before a hcf poll is detected. 31:16 res reserved bit name description 7:0 sifs_time sifs_time is the number of s in sifs. for example, in 802.11a, sifs_time woul d be set to 16. this value is used to determine quiet collision and filtering due to tbtt and txop limits. 11:8 tx_latency tx_latency is the latency in s from tx_frame being asserted by the mac to when the energy of the frame is on the air. this value is used to decrease the time to tbtt and time remaining in txop in the calculation to determine quiet collision. 14:12 ack_shift ack_shift is used to generate the ack_time, which is used to generate the ack_sifs_time. the ack_time table in the hardware assumes a channel width of 2.5 mhz. this value should be 3 for cck rates. 02.5 mhz 15 mhz 31:15 res reserved bit name description 7:0 sifs_time txop in units of 32 s. a txop value exists for each qos tid value. when a new burst starts, the tid is used to select one of the 16 txop values. this txop decrements until the end of the burst to make sure that the packets are not sent out by the time txop expi res. txopx is used for legacy non qos bursting. 31:8 res reserved do not copy free datasheet http://www.datasheet-pdf.com/
atheros communications, inc. AR9223 single-chip 2x2 mimo mac/bb/radio for 802.11n wlans ? 115 company confidential october 2009 ? 115 6.2.9.55 txop for tid 0 to 3 (mac_pcu_txop_0_3) offset: 0x081f0 access: hardware = read-only software = read/write reset value: 0x0 6.2.9.56 txop for tid 4 to 7 (mac_pcu_txop_4_7) offset: 0x081f4 access: hardware = read-only software = read/write reset value: 0x0 6.2.9.57 txop for tid 8 to 11 (mac_pcu_txop_8_11) offset: 0x081f8 access: hardware = read-only software = read/write reset value: 0x0 6.2.9.58 txop for tid 0 to 3 (mac_pcu_txop_12_15) offset: 0x081fc access: hardware = read-only software = read/write reset value: 0x0 bit name description 7:0 value_0 value in units of 32 s 15:8 value_1 value in units of 32 s 23:16 value_2 value in units of 32 s 31:24 value_3 value in units of 32 s bit name description 7:0 value_4 value in units of 32 s 15:8 value_5 value in units of 32 s 23:16 value_6 value in units of 32 s 31:24 value_7 value in units of 32 s bit name description 7:0 value_8 value in units of 32 s 15:8 value_9 value in units of 32 s 23:16 value_10 value in units of 32 s 31:24 value_11 value in units of 32 s bit name description 7:0 value_12 value in units of 32 s 15:8 value_13 value in units of 32 s 23:16 value_14 value in units of 32 s 31:24 value_15 value in units of 32 s do not copy free datasheet http://www.datasheet-pdf.com/
116 ? AR9223 single-chip 2x2 mimo mac/bb/radio for 802.11n wlans atheros communications, inc. 116 ? october 2009 company confidential 6.2.9.59 generic timers (mac_pcu_generic_timers[0:15]) offset: 0x08200 access: hardware = read/write software = read/write reset value: 0x0 note: generic _timer_0, unlike other generic timers, does not wake the mac before timer expiration and its overflow mechanism does not generate an interrupt. instead, it silently adds this period repeatedly until the next timer has advanced past the tsf. thus when mac wakes after sleeping for multiple tbtts, the tgbtt does not assert repeatedly or cause the beacon miss count to jump. 6.2.9.60 generic timers mode (mac_pcu_generic_timers_mode) offset: 0x08240 access: hardware = read/write software = read/write reset value: 0x00100000 6.2.9.61 32 khz sleep mode (mac_pcu_slp32_mode) offset: 0x08244 access: hardware = read-only software = read/write reset value: see field description address default description 0x8200? 0x821c 0x0 generic_timer_next 0x8220? 0x823c 0x0 generic_timer_period generic timer function 0tbtt 1 dma beacon alert 2 sw beacon alert 3 hcf trigger timer 4next_tim 5next_dtim 6 quiet time trigger 7 no dedicated function bit name description 7:0 enable 10:8 overflow_index indicates the last generic timer that overflowed 31:11 thresh number of s that generate a threshold interr upt if exceeded in tsf comparison bit name description 19:0 half_clk_latency time in s from the detection of the falling edge of the 32 khz clk to the rising edge of the 32 khz clk. reset value: 0xf424 20 enable when set, indicates that the tsf should be allowed to increment on its own. reset value: 0x1 21 tsf_write_status the tsf write status. reset value: 0x1 22 disable_32khz indicates the 32 kh z clock is not used to contro l the tsf, but the mac clock increments the tsf. only used on ap class devices that do not go to sleep. reset value: 0x0 31:23 res reserved do not copy free datasheet http://www.datasheet-pdf.com/
atheros communications, inc. AR9223 single-chip 2x2 mimo mac/bb/radio for 802.11n wlans ? 117 company confidential october 2009 ? 117 6.2.9.62 32 khz sleep wake (mac_pcu_slp32_wake) offset: 0x08248 access: hardware = read-only software = read/write reset value: 0x800 6.2.9.63 32 khz sleep increment (mac_pcu_slp32_inc) offset: 0x0824c access: hardware = read-only software = read/write reset value: 0x1e848 6.2.9.64 sleep mib sleep count (mac_pcu_slp_mib1) offset: 0x08250 access: hardware = read/write software = read/write reset value: 0x0 6.2.9.65 sleep mib cycle count (mac_pcu_slp_mib2) offset: 0x08254 access: hardware = read/write software = read/write reset value: 0x0 bit name description 15:0 xtl_time time in s before a generic timer should expi re that the wake signal asserts to the crystal wake logic. add an extra 31 s due to 32 khz clock resolution. bit name description 19:0 tsf_inc time in 1/2 12 of a s the tsf increments on the rising edge of the 32 khz clk (30.5176 s period). the upper 8 bits are at s resolution. the lower 12 bits are the fractional portion. 1 unit x ________ = __________ 1/212 ms 30.5176 ms where x = 125000, or 0x1e848 is the defaul t setting for 32.768 mhz clock. 31:20 res reserved bit name description 31:0 sleep_cnt counts the number of 32 khz clock cycles that the mac has been asleep bit name description 31:0 cycle_cnt counts the absolute number of 32 khz clock cycles. when cycle_cnt bit 31 is 1, the mib interrupt will be asserted. sleep_cnt and cycle_cnt are saturating counters when the value of cycle_cnt reaches 0xffff_ffff both counters will stop incrementing. do not copy free datasheet http://www.datasheet-pdf.com/
118 ? AR9223 single-chip 2x2 mimo mac/bb/radio for 802.11n wlans atheros communications, inc. 118 ? october 2009 company confidential 6.2.9.66 sleep mib control status (mac_pcu_slp_mib3) offset: 0x08258 access: hardware = read/write software = read/write reset value: 0x0 6.2.9.67 global mode (mac_pcu_20_40_mode) offset: 0x08318 access: hardware = read-only software = read/write reset value: 0x0 6.2.9.68 difference rx_clear counter (mac_pcu_rx_clear_diff_cnt) offset: 0x08328 access: hardware = read-only software = read/write reset value: 0x0 bit name description 0 clr_cnt clr_cnt clears both sleep_cnt and cycle_cnt. pending is asserted while the clearing of these registers is pending. 1 pending sleep_cnt, cycle_cnt, and clr_cnt are writable for diagnostic purposes. before every read/write, the pending bit should be polled to verify any pending write has cleared. 31:2 res reserved bit name description 0 joined_rx_clear setting this bit causes the rx_cle ar used in the mac to be the and of the control channel rx_clear and the extension channel rx_clear. if this bit is clear then the mac will use only the control channel rx_clear. 31:1 res reserved bit name description 31:0 rx_clear_diff_cnt a cycle counter mib register. on every cycle of the ma c clock, this counter increments every time the extension cha nnel rx_clear is low when the mac is not actively transmitting or receiving. due to a small lag between tx_frame and rx_clear as well as between rx_c lear and rx_frame, the count may have some residual value even when no ac tivity is on the extension channel. do not copy free datasheet http://www.datasheet-pdf.com/
atheros communications, inc. AR9223 single-chip 2x2 mimo mac/bb/radio for 802.11n wlans ? 119 company confidential october 2009 ? 119 6.2.9.69 control registers for block ba control fields (mac_pcu_ba_bar_control) offset: 0x08330 access: hardware = read-only software = read/write reset value: see field description 6.2.9.70 legacy plcp spoof (mac_pcu_legacy_plcp_spoof) offset: 0x08334 access: hardware = read-only software = read/write reset value: see field description 6.2.9.71 phy error mask and eifs mask (mac_pcu_phy_error_mask_cont) offset: 0x08338 access: hardware = read-only software = read/write reset value: 0x0 bit name description 3:0 compressed_offset indicates the bit offset in the block ack or block ack request control field which defines the location of the compressed bit. reset value: 0x2 7:4 ack_policy_offset indicates the bit offset in the block ack or block ack request control field which defines the location of the ack policy bit. reset value: 0x0 8 compressed_value the value of the compressed bit. reset value: 0x1 9 ack_policy_value the value of the ack policy bit. reset value: 0x1 31:10 res reserved bit name description 7:0 eifs_minus_difs defines the number of s to be subtracted from the transmit packet duration to provide fairness for legacy devices as well as ht devices. reset value: 0x0 12:8 min_length this register defines the minimum spoofed legacy plcp length. reset value: 0xe 31:9 res reserved bit name description 7:0 mask_value continuation of register mac_pcu_phy_error_mask_value. bits [2], [1], and [0] correspond to phy er rors 34, 33, and 32. all others phy errors above 39 will be filtered. 15:8 res reserved 23:16 eifs_value continuation of register mac_pcu_phy_error_mask_value. bits [2], [1], and [0] correspond to phy er rors 34, 33, and 32. all others phy errors above 39 cause eifs delay. 31:19 res reserved do not copy free datasheet http://www.datasheet-pdf.com/
120 ? AR9223 single-chip 2x2 mimo mac/bb/radio for 802.11n wlans atheros communications, inc. 120 ? october 2009 company confidential 6.2.9.72 tx timer (mac_pcu_tx_timer) offset: 0x0833c access: hardware = read/write software = read/write reset value: 0x0 6.2.9.73 key cache (mac_pcu_key_cache[0:1023]) offset: 0x08800 access: hardware = read-only software = read/write reset value: 0x0 when the key type is 4 (tkip) and key is valid, this entry + 64 contains the michael key. tkip keys are not allowed to reside in the entries 64?127 because they require the michael key. entries 64?67 are always reserved for michael. note: internally this memory is 50 bits wide, thus to write a line of the memory requires two 32-bit writes. all writes to registers with an offset of 0x0 or 0x8 actually write to a temporary holding register. a write to register with an offset of 0x4 or 0xc writes to the memory with the current write value concatenated with the temporary holding register. bit name description 14:0 tx_timer guarantees the tran smit frame does not take more time than the values programmed in this timer. the unit for this timer is in s. 15 tx_timer_enable enabled when this bit is set to 1. 31:16 res reserved table 6-15. offset to first dword of n th key [1] [1]key = (pci address: 8800 + 20* n ) intra key offset bits description 8* n + 00 31:0 key[31:0] 8* n + 04 15:0 key[47:32] 8* n + 08 31:0 key[79:48] 8* n + 0c 15:0 key[95:79] 8* n + 10 31:0 key[127:96] 8* n + 14 2:0 key type: 0 40b 1 104b 2 tkip without mic 3 128b 4tkip 5 reserved 6 aes_ccm 7 do nothing 8* n + 14 14:3 reserved 8* n + 18 31:0 addr[32:1] 8* n + 1c 14:0 addr[47:33] 15 key valid 17:16 key id table 6-16. offset to first dword of n th key (continued) intra key offset bits description 8* n + 800 31:0 rx michael key 0 8* n + 804 15:0 tx michael key 0 [31:16] 8* n + 808 31:0 rx michael key 1 8* n + 80c 15:0 tx michael key 0 [15:0] 8* n + 810 31:0 tx michael key 1 8* n + 814 res reserved 8* n + 818 res reserved 8* n + 81c res reserved 15 key valid = 0 do not copy free datasheet http://www.datasheet-pdf.com/
atheros communications, inc. AR9223 single-chip 2x2 mimo mac/bb/radio for 802.11n wlans ? 121 company confidential october 2009 ? 121 7. electrical characteristics 7.1 absolute maximum ratings table 7-1 summarizes the absolute maximum ratings and table 7-2 lists the recommended operating conditions for the AR9223. absolute maximum ratings are those values beyond which damage to the device can occur. functional operation un der these conditions, or at any other condition beyond those indicated in the operational sections of this document, is not recommended. 7.2 recommended operating conditions table 7-1. absolute maximum ratings symbol parameter max rating unit v dd12 supply voltage ?0.3 to 1.8 v v dd33 maximum i/o supply voltage ?0.3 to 4.0 v rf in maximum rf input (reference to 50 )+10dbm t store storage temperature ?60 to 150 c t j junction temperature 125 c esd electrostatic disc harge tolerance 2000 v electrostatic discharge tolerance (xtalo and xtali pins) 1500 v table 7-2. recommended operating conditions symbol parameter conditions min typ max unit v dd12 supply voltage [1] 5% 1.14 1.2 1.26 v v dd33 i/o voltage 10% 2.97 3.3 3.63 v t case case temperature ? 0 ? 95 c psi jt thermal parameter [2] ???2. 0 c/w [1]since the 1.2 v supply is derived from 3.3 v, the AR9223 expects that 1.2 v lags 3.3 v. [2]for 12x12 mm bga package. do not copy free datasheet http://www.datasheet-pdf.com/
122 ? AR9223 single-chip 2x2 mimo mac/bb/radio for 802.11n wlans atheros communications, inc. 122 ? october 2009 company confidential figure 7-1 shows the supply voltage ramp-up and reset timing diagram. 7.3 40 mhz clock characteristics when using an external clock, the xtali pin is grounded and the xtalo pin should be driven with a square wave clock. the dc voltage level of xtalo should be approximately 0.6 v. the external clock driving xtalo must have sharp rise and fall times to reduce jitter. figure 7-1. voltage ramp-up and reset timing table 7-3. 40 mhz clock characteristics symbol parameter conditions min typ max unit v ih input high voltage ? 1 ? 3.3 v v il input low voltage ? ?0.2 ? 0.2 v t dcycle duty cycle ? 40 50 60 % t rise clock rise time ? ??2ns t fall clock fall time ? ? ? 2 ns do not copy free datasheet http://www.datasheet-pdf.com/
atheros communications, inc. AR9223 single-chip 2x2 mimo mac/bb/radio for 802.11n wlans ? 123 company confidential october 2009 ? 123 7.4 radio characteristics the following conditions apply to the typical characteristics unless otherwise specified: v dd2 = 1.2 v v dd3 = 3.3 v, t amb = 25 c 7.4.1 receiver characteristics table 7-3 summarizes the AR9223 receiver characteristics. table 7-4. receiver characteristics for 2.4 ghz operation symbol parameter conditions min typ max unit f rx receive input frequency range 5 mhz center frequency 2.412 ? 2.472 ghz nf receive chain noise figure (max gain) see note [1] ?4.5?db s rf sensitivity cck, 1 mbps see note [2] ?80 ?96 ? dbm cck, 11 mbps ?76 ?91 ? ofdm, 6 mbps ?82 ?95 ? ofdm, 54 mbps ?65 ?81 ? ht20, mcs0, 1 stream, 1 tx, 1 rx see note [2] ?82 ?95 ? dbm ht20, mcs7, 1 stream, 1 tx, 1 rx ?64 ?77 ? ht20, mcs8, 2 stream, 2 tx, 2 rx ?82 ?94 ? ht20, mcs15, 2 stream, 2 tx, 2 rx ?64 ?75 ? ht40, mcs0, 1 stream, 1 tx, 1 rx see note [2] ?79 ?92 ? dbm ht40, mcs7, 1 stream, 1 tx, 1 rx ?61 ?75 ? ht40, mcs8, 2 stream, 2 tx, 2 rx ?79 ?91 ? ht40, mcs15, 2 stream, 2 tx, 2 rx ?61 ?71 ? ip1db input 1 db compression (min. gain) ? ? ?8 ? dbm iip3 input third intercept point (min. gain) ? ? 5 ? dbm z rfin_input recommended lna differential drive impedance ch 0, ch 1 ? 16?j23 [3] ? er phase i,q phase error ? ? 1 [4] ? eramp i,q amplitude error ? ? 0.1 [4] ?db r adj adjacent channel rejection cck 10 to 20 mhz [5] 35 36 ? db ofdm, 6 mbps 16 36 ? ofdm, 54 mbps ?1 26 ? ht20, mcs0 10 to 20 mhz [5] 16 35 ? db ht20, mcs7 ?2 23 ? ht20, mcs8 16 36 ? ht20, mcs15 ?220? trpowup time for power up (from synthesizer on) ? ? 1.5 ? s [1]for improved sensitivity performa nce, an external lna may be used. [2]sensitivity performance based on at heros reference design, wh ich includes tx/rx antenna switch, and xlna. minimum values based on ieee 802.11 specifications. [3]estimated value. [4]iq phase error and iq amplitude error are analog values prior to digital correction. [5]typical values measured with reference design. minimum values based on ieee 802.11 specifications. do not copy free datasheet http://www.datasheet-pdf.com/
124 ? AR9223 single-chip 2x2 mimo mac/bb/radio for 802.11n wlans atheros communications, inc. 124 ? october 2009 company confidential 7.4.2 transmitter characteristics table 7-4 summarizes the transmitter characteristics for the AR9223. table 7-5. transmitter characteristi cs for 2.4 ghz operation symbol parameter conditions min typ max unit f tx transmit output frequency range 5 mhz center frequency 2.412 ? 2.472 ghz p out mask compliant cck output power see note [1] [1]measured using the balun/xpa recommended by atheros under closed-loop power control. ?17?dbm evm compliant ofdm output power for 64 qam see note [1] ?17?dbm ht20, mcs15 ? ? 15 ? dbm ht40, mcs15 ? 14 ? sp gain pa gain step see note [2] [2]guaranteed by design. ?0.5?db a pl accuracy of power leveling loop see notes [3] [4] [3]manufacturing calibration required. [4]not including tolerance of external pow er detector and its temperature variation. ?0.5? db z rfout_load recommended differential pa load impedance see notes [5] [5]see the impedance matching circuit in the atheros refe rence design schematics. to achieve good rf performance, it is strongly recommended not to alter the rf portion of the atheros reference desi gn for different matching networks. ? 135+j24 ? op1db output p1db (max. gain) 2.442 ghz ? 11 ? dbm oip3 output third order intercept point (max. gain) 2.442 ghz ? 20 ? dbm ss sideband suppression ? ? ?37 ? dbc rs synthesizer reference spur: ? ? ?63 ? dbc tx mask transmit spectral mask cck at 11 mhz offset see note [6] [6]measured at the antenna connector port. average con ducted transmit power levels = 17 dbm for cck and ofdm, 16 dbm for ht20 and ht40. system includes external pa . maximum values based on ieee 802.11 specifications. ? ?38 ?30 dbr at 22 mhz offset ? ?53 ?50 ofdm at 11 mhz offset see note [6] ? ?25 ?20 dbr at 20 mhz offset ? ?39 ?28 at 30 mhz offset ? ?47 ?40 ht20 at 11 mhz offset see note [6] ? ?24 ?20 dbr at 20 mhz offset ? ?39 ?28 at 30 mhz offset ? ?48 ?40 ht40 at 21 mhz offset see note [6] ? ?27 ?20 dbr at 40 mhz offset ? ?39 ?28 at 60 mhz offset ? ?49 ?45 ttpowup time for power up (from synthesizer on) ? ? 1.5 ? s do not copy free datasheet http://www.datasheet-pdf.com/
atheros communications, inc. AR9223 single-chip 2x2 mimo mac/bb/radio for 802.11n wlans ? 125 company confidential october 2009 ? 125 7.4.3 synthesizer characteristics table 7-5 summarizes the synthesizer characteristics for the AR9223. 7.5 power consumption parameters the following conditions apply to the typical characteristics unless otherwise specified: v dd2 = 1.2 v v dd3 = 3.3 v, t amb = 25 c table 7-6 shows the typical power drain on each of the four on-chip power supply domains as a function of the AR9223?s operating mode. table 7-6. synthesizer composite characteristics for 2.4 ghz operation symbol parameter conditions min typ max unit pn phase noise (at tx_out) at 30 khz offset ? ?101 ? dbc/ hz at 100 khz offset ? ?103 ? at 500 khz offset ? ?110 ? at 1 mhz offset ? ?114 ? f c center channel frequency center frequency at 5 mhz spacing [1] [1]frequency is measured at the tx output. 2.412 ? 2.472 ghz f ref reference oscillator frequency 20 ppm [2] [2]over temperature variation and aging. ?40?mhz ts powup time for power up (from sleep) ? ? 200 ? s table 7-7. power consumption for 2.4 ghz operation operating mode 3.3 v supply (ma) 1.2 v supply (ma) sleep 3 6 idle (two-chain rx) 69 225 tx (two-chain) 173 195 rx (two-chain) 97 310 do not copy free datasheet http://www.datasheet-pdf.com/
126 ? AR9223 single-chip 2x2 mimo mac/bb/radio for 802.11n wlans atheros communications, inc. 126 ? october 2009 company confidential do not copy free datasheet http://www.datasheet-pdf.com/
atheros communications, inc. AR9223 single-chip 2x2 mimo mac/bb/radio for 802.11n wlans ? 125 company confidential october 2009 ? 125 8. ac specifications 8.1 pci interface timing the AR9223 pci interface supports pci 2.3 standards. refer to the applicable standard for further details. 8.2 pci_clk specifications the clock waveform delivered to the AR9223, as measured at the AR9223 input pins must meet the specifications shown in figure 8-1 and table 8-1 . 8.3 pci clock specifications table 8-1 depicts the clock specifications. figure 8-1. pci interface clock waveform t_low t_high 0.5 vcc 0.4 vcc 0.3 vcc 0.4 vcc, p-to-p (minimum) 0.6 vcc 0.2 vcc table 8-1. clock specifications symbol parameter 66 mhz 33 mhz units min max min max t cyc clk cycle time 15 30 30 ns t high clk high time 6 ? 11 ? ns t low clk low time 6 ? 11 ? ns ? clk slew rate 1.5 4 1 4 v/ns do not copy free datasheet http://www.datasheet-pdf.com/
126 ? AR9223 single-chip 2x2 mimo mac/bb/radio for 802.11n wlans atheros communications, inc. 126 ? october 2009 company confidential 8.3.10 pci timing parameters table 8-2 provides the timing parameters for the AR9223 pci interface. 8.4 eeprom timing figure 8-2 defines the timing parameters for the eeprom interface. table 8-2. pci timing parameters symbol parameter 66 mhz 33 mhz units min max min max t val clk to signal valid delay bussed signals 26211ns t val (ptp) clk to signal valid delay point-to-point signals 26212ns t su input setup time to clk bussed signals 3?7?ns t su (ptp) input setup time to clk point-to-point signals [1] 5 ? 10, 12 ? ns t h input hold time from clk 0 ? 0 ? ns [1]pci_req_l and pci_gnt_l are point-to-point signals with differing output valid delay and input setup times from bussed signals. pci_gnt_l has a set up of 10; pci_req_l has a setup of 12. all other signals are bussed. symbol parameter min max unit t sck eprm_sck cycle time 33 mhz pci 15.36 s 66 mhz pci 7.68 s t high high time of eprm_sck (parameter scales with t sck ) 0.35 * t sck 0.40 * t sck s t w_val write data valid from falling edge eprm_sck (parameter scales with t sck ) 0.10 * t sck 0.15 * t sck s t r_su read data setup time to risi ng edge of eprm_sck 50 ? ns t r_h read data hold time from rising edge of eprm_sck 50 ? ns figure 8-2. eeprom interface timing do not copy free datasheet http://www.datasheet-pdf.com/
atheros communications, inc. AR9223 single-chip 2x2 mimo mac/bb/radio for 802.11n wlans ? 127 company confidential october 2009 ? 127 9. package dimensions the AR9223 bga-337 package drawings and dimensions are provided in figure 9-1 and table 9-1 . figure 9-1. package details top view side view bottom view detail "a" detail "b" do not copy free datasheet http://www.datasheet-pdf.com/
128 ? AR9223 single-chip 2x2 mimo mac/bb/radio for 802.11n wlans atheros communications, inc. 128 ? october 2009 company confidential table 9-1. package dimensions dimension label min nom max unit min nom max unit a 0.77 0.96 1.14 mm 0.030 0.037 0.045 inches a1 0.16 0.22 0.28 mm 0.006 0.008 0.011 inches a2 0.61 0.74 0.86 mm 0.024 0.029 0.033 inches b 0.25 0.30 0.35 mm 0.010 0.012 0.014 inches d/e 11.90 12.00 12.10 mm 0.468 0.472 0.476 inches d1/e1 ? 11.00 ? mm ? 0.433 ? inches e ? 0.50 ? mm ? 0.020 ? inches aaa 0.10 mm 0.004 inches bbb 0.10 mm 0.004 inches ddd 0.08 mm 0.003 inches eee 0.15 mm 0.006 inches fff 0.05 mm 0.002 inches md/me 23/23 23/23 [1]controlling dime nsion: millimeters. [2]primary datum c and seating plane are defined by the spherical crowns of the solder balls. [3]dimension b is measured at the maximum solder ball diameter, parallel to primary datum c. [4]there shall be a minimum clearance of 0.25 mm betwee n the edge of the solder ball and the body edge. [5]reference document: jedec mo-195. [6]the pattern of pin 1 fiduci al is for reference only. [7]special characterist ics c class: bbb, ddd. do not copy free datasheet http://www.datasheet-pdf.com/
atheros communications, inc. AR9223 single-chip 2x2 mimo mac/bb/radio for 802.11n wlans ? 129 company confidential october 2009 ? 129 10.ordering information the order number AR9223-ac1a specifies a lead-free standard-temperature version of the AR9223. the order number AR9223-ac2a specifies a halogen-free standard-temperature version of the AR9223. do not copy free datasheet http://www.datasheet-pdf.com/
atheros communications, incorporated 5480 great america parkway santa clara, ca 95054 t: 408/773-5200 f: 408/773-9940 www.atheros.com the information in this document has been ca refully reviewed and is believed to be accurate. nonetheless, this document is subj ect to change without notice. atheros assumes no responsibility for any inaccuracies that may be contai ned in this document, and makes no commitment to update or to keep current th e contained information, or to notify a pers on or organization of any updates. athero s reserves the right to make changes, at any time, to improve reliability, function or design and to attempt to supply the best product po ssible. document number: 981-00078-001 mkg-0727 rev. 4 do not copy free datasheet http://www.datasheet-pdf.com/

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